d2/d55/grtos__hw_8tcl_source.html

# TCL File Generated by Component Editor 12.1

# Tue Nov 12 11:07:55 GFT 2013

# DO NOT MODIFY


# PONER PARAMETRO CLOCK_RATE de SYSTEM_INFO

#Ej: set_parameter_property <my_parameter> SYSTEM_INFO {CLOCK_RATE <my_clk>}


#

# grtos "gRTOS" v1.0

# Ricardo_Cayssials 2013.11.12.11:07:55

# gRTOS Qsys Component

#


#

# request TCL package from ACDS 12.1

#

package require -exact qsys 13.0


#

# module grtos

#

set_module_property DESCRIPTION "gRTOS Qsys Component"

set_module_property NAME grtos

set_module_property VERSION 1.0

set_module_property INTERNAL false

set_module_property OPAQUE_ADDRESS_MAP true

set_module_property GROUP gRTOS

set_module_property AUTHOR "Ricardo Cayssials"

set_module_property DISPLAY_NAME gRTOS

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL AUTO

set_module_property REPORT_TO_TALKBACK false

set_module_property ALLOW_GREYBOX_GENERATION false


# from https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06242008_7.html

# from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qsys_components.pdf

# add_fileset_file my_custom_component.qxp QXP PATH "my_custom_component.qxp"


#

# file sets

#

add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"

set_fileset_property quartus_synth TOP_LEVEL grtos

set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false

add_fileset_file grtos.qxp QXP PATH grtos.qxp

# add_fileset_file STD_FIFO.vhd VHDL PATH STD_FIFO.vhd


add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation"

set_fileset_property sim_verilog TOP_LEVEL grtos

set_fileset_property sim_verilog ENABLE_RELATIVE_INCLUDE_PATHS false

add_fileset_file grtos.qxp QXP PATH grtos.qxp

# add_fileset_file STD_FIFO.vhd VHDL PATH STD_FIFO.vhd


add_fileset sim_vhdl SIM_VHDL "" "VHDL Simulation"

set_fileset_property sim_vhdl TOP_LEVEL grtos

set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false

add_fileset_file grtos.qxp QXP PATH grtos.qxp

# add_fileset_file STD_FIFO.vhd VHDL PATH STD_FIFO.vhd


#

# parameters

#

# Number of Processors

add_parameter NProcessors INTEGER 1 "Number of System Processors"

set_parameter_property NProcessors DEFAULT_VALUE 1

set_parameter_property NProcessors DISPLAY_NAME "Number of Processors"

set_parameter_property NProcessors TYPE INTEGER

set_parameter_property NProcessors UNITS None

set_parameter_property NProcessors ALLOWED_RANGES {1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32}

set_parameter_property NProcessors DESCRIPTION "Number of System Processors"

set_parameter_property NProcessors HDL_PARAMETER false


# Prescaler

add_parameter PreScale INTEGER 31 "Time Prescaler"

set_parameter_property PreScale DEFAULT_VALUE 31

set_parameter_property PreScale DISPLAY_NAME "Time Prescaler"

set_parameter_property PreScale TYPE INTEGER

set_parameter_property PreScale UNITS None

set_parameter_property PreScale ALLOWED_RANGES {1:1073741824}

set_parameter_property PreScale DESCRIPTION "Time Scale division"

set_parameter_property PreScale HDL_PARAMETER false


add_parameter PROCESSOR_TYPE STRING "" "Processor type"

set_parameter_property PROCESSOR_TYPE HDL_PARAMETER false


add_parameter INSTRUCTION_CACHE_SIZE STRING "None" "Instruction cache size"

set_parameter_property INSTRUCTION_CACHE_SIZE HDL_PARAMETER false


add_parameter INSTRUCTION_CACHE_BURST STRING "Disable" "Add burstcount signal to instruction_master"

set_parameter_property INSTRUCTION_CACHE_BURST HDL_PARAMETER false


add_parameter ENABLE_HPS_MAP_ACCESS BOOLEAN false

set_parameter_property ENABLE_HPS_MAP_ACCESS HDL_PARAMETER false


add_parameter NIOS_CLOCK_FREQUENCY INTEGER

set_parameter_property NIOS_CLOCK_FREQUENCY HDL_PARAMETER false


add_parameter BUS_CLOCK_FREQUENCY INTEGER

set_parameter_property BUS_CLOCK_FREQUENCY HDL_PARAMETER false


add_parameter BUS_WIDTH INTEGER

set_parameter_property BUS_WIDTH HDL_PARAMETER false


add_parameter EXTERNAL_MEMORY_SPAN INTEGER 4

set_parameter_property EXTERNAL_MEMORY_SPAN HDL_PARAMETER false


add_parameter EXTERNAL_MEMORY_UNIT STRING ""

set_parameter_property EXTERNAL_MEMORY_UNIT HDL_PARAMETER false


#

# display items

#

add_display_item "" "System Properties" GROUP ""

add_display_item "" Interrupt GROUP ""


#

# connection point clock_reset

#

add_interface clock_reset clock end

set_interface_property clock_reset clockRate 0

set_interface_property clock_reset ENABLED true


add_interface_port clock_reset clk clk Input 1


# SYSTEM_INFO de https://www.intel.com/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/qts/qsys_tcl.pdf

add_parameter GRTOS_CLOCK_FREQUENCY INTEGER

set_parameter_property GRTOS_CLOCK_FREQUENCY SYSTEM_INFO {CLOCK_RATE clock_reset}

add_display_item "" GRTOS_CLOCK_FREQUENCY PARAMETER

set_parameter_property GRTOS_CLOCK_FREQUENCY HDL_PARAMETER false


add_parameter GRTOS_CLOCK_RESET_INFO STRING

set_parameter_property GRTOS_CLOCK_RESET_INFO SYSTEM_INFO {CLOCK_RESET_INFO clock_reset}

add_display_item "" GRTOS_CLOCK_RESET_INFO PARAMETER

set_parameter_property GRTOS_CLOCK_RESET_INFO HDL_PARAMETER false


add_parameter GRTOS_GENERATION_ID INTEGER

set_parameter_property GRTOS_GENERATION_ID SYSTEM_INFO {GENERATION_ID}

add_display_item "" GRTOS_GENERATION_ID PARAMETER

set_parameter_property GRTOS_GENERATION_ID HDL_PARAMETER false

#

# connection point clock_reset_reset

#

add_interface clock_reset_reset reset end

set_interface_property clock_reset_reset associatedClock clock_reset

set_interface_property clock_reset_reset synchronousEdges DEASSERT

set_interface_property clock_reset_reset ENABLED true


add_interface_port clock_reset_reset reset reset Input 1


# *************************************************************

# *************************************************************

#

# connection point clk_out

#

add_interface clk_out clock start

set_interface_property clk_out associatedDirectClock ""

set_interface_property clk_out clockRate 0

# set_interface_property clk_out clockRateKnown false

set_interface_property clk_out ENABLED true

set_interface_property clk_out EXPORT_OF ""

set_interface_property clk_out PORT_NAME_MAP ""

set_interface_property clk_out SVD_ADDRESS_GROUP ""


add_interface_port clk_out clk_out clk Output 1


#

# connection point s_Global

#

add_interface s_Global avalon end

set_interface_property s_Global addressUnits WORDS

set_interface_property s_Global associatedClock clock_reset

set_interface_property s_Global associatedReset clock_reset_reset

set_interface_property s_Global bitsPerSymbol 8

set_interface_property s_Global burstOnBurstBoundariesOnly false

set_interface_property s_Global burstcountUnits WORDS

set_interface_property s_Global explicitAddressSpan 0

set_interface_property s_Global holdTime 0

set_interface_property s_Global linewrapBursts false

set_interface_property s_Global maximumPendingReadTransactions 0

set_interface_property s_Global readLatency 0

set_interface_property s_Global readWaitStates 0

set_interface_property s_Global readWaitTime 0

set_interface_property s_Global setupTime 0

set_interface_property s_Global timingUnits Cycles

set_interface_property s_Global writeWaitTime 0

set_interface_property s_Global ENABLED true


add_interface_port s_Global slave_gRTOS_address address Input 7

add_interface_port s_Global slave_gRTOS_read read Input 1

add_interface_port s_Global slave_gRTOS_write write Input 1

add_interface_port s_Global slave_gRTOS_readdata readdata Output 32

add_interface_port s_Global slave_gRTOS_writedata writedata Input 32

add_interface_port s_Global slave_gRTOS_waitrequest waitrequest Output 1

# add_interface_port s_Global slave_gRTOS_chipselect chipselect Input 1

set_interface_assignment s_Global embeddedsw.configuration.isFlash 0

set_interface_assignment s_Global embeddedsw.configuration.isMemoryDevice 0

set_interface_assignment s_Global embeddedsw.configuration.isNonVolatileStorage 0

set_interface_assignment s_Global embeddedsw.configuration.isPrintableDevice 0


set i 1


#

# connection point interrupt receiver

#


#  Dummy master port

    add_interface dummy_master avalon start

    set_interface_property dummy_master burstOnBurstBoundariesOnly false

    set_interface_property dummy_master doStreamReads false

    set_interface_property dummy_master doStreamWrites false

    set_interface_property dummy_master linewrapBursts false

    set_interface_property dummy_master ASSOCIATED_CLOCK clock_reset

    set_interface_property dummy_master ENABLED true


   add_interface_port dummy_master avm_m1_address address Output 32

   add_interface_port dummy_master avm_m1_writedata writedata Output 32

   add_interface_port dummy_master avm_m1_readdata readdata Input 32


    add_interface_port dummy_master avm_m1_read read Output 1

    add_interface_port dummy_master avm_m1_write write Output 1

    add_interface_port dummy_master avm_m1_waitrequest waitrequest Input 1


#  Interrupt input port

    add_interface interrupt_receiver interrupt start

    set_interface_property interrupt_receiver irqScheme INDIVIDUAL_REQUESTS

    set_interface_property interrupt_receiver ASSOCIATED_CLOCK clock_reset

    set_interface_property interrupt_receiver associatedAddressablePoint dummy_master

    set_interface_property interrupt_receiver ENABLED true


    add_interface_port interrupt_receiver DIRQI irq Input 32


    # Get the interrupts connected to the GRTOS

    add_parameter GRTOS_INTERRUPTS LONG

    set_parameter_property GRTOS_INTERRUPTS SYSTEM_INFO {INTERRUPTS_USED interrupt_receiver}

    add_display_item "" GRTOS_INTERRUPTS PARAMETER


set_module_property VALIDATION_CALLBACK validate

set_module_property ELABORATION_CALLBACK elaborate


proc validate {} {

  set_module_assignment embeddedsw.CMacro.NPROCESSORS [get_parameter_value NProcessors]

  set_module_assignment embeddedsw.CMacro.PRESCALE [get_parameter_value PreScale]

  set_module_assignment embeddedsw.CMacro.GRTOSFREQUENCY [get_parameter_value GRTOS_CLOCK_FREQUENCY]

  set_module_assignment embeddedsw.CMacro.GRTOSINTERRUPTS [get_parameter_value GRTOS_INTERRUPTS]

  set_module_assignment embeddedsw.CMacro.GRTOSCLOCKRESETINFO [get_parameter_value GRTOS_CLOCK_RESET_INFO]

  set_module_assignment embeddedsw.CMacro.GRTOSGENERATIONID [get_parameter_value GRTOS_GENERATION_ID]


  # #########################

  set_module_assignment embeddedsw.CMacro.PROCESSOR_TYPE [get_parameter_value PROCESSOR_TYPE]

  set_module_assignment embeddedsw.CMacro.INSTRUCTION_CACHE_SIZE [get_parameter_value INSTRUCTION_CACHE_SIZE]

  set_module_assignment embeddedsw.CMacro.INSTRUCTION_CACHE_BURST [get_parameter_value INSTRUCTION_CACHE_BURST]

  set_module_assignment embeddedsw.CMacro.ENABLE_HPS_MAP_ACCESS [get_parameter_value ENABLE_HPS_MAP_ACCESS]

  set_module_assignment embeddedsw.CMacro.NIOS_CLOCK_FREQUENCY [get_parameter_value NIOS_CLOCK_FREQUENCY]

  set_module_assignment embeddedsw.CMacro.BUS_CLOCK_FREQUENCY [get_parameter_value BUS_CLOCK_FREQUENCY]

  set_module_assignment embeddedsw.CMacro.BUS_WIDTH [get_parameter_value BUS_WIDTH]

  set_module_assignment embeddedsw.CMacro.EXTERNAL_MEMORY_SPAN [get_parameter_value EXTERNAL_MEMORY_SPAN]

  set_module_assignment embeddedsw.CMacro.EXTERNAL_MEMORY_UNIT [get_parameter_value EXTERNAL_MEMORY_UNIT]

  # #########################


  set j 2

  #set_module_assignment embeddedsw.CMacro.PROPIERTIES [get_interface_properties slv_irq4]


  # EIC port identification for BSP tools

  set_interface_assignment s_Global embeddedsw.configuration.isInterruptControllerReceiver 1

  set_interface_assignment s_Global embeddedsw.configuration.transportsInterruptsFromReceivers s_Global

}


proc elaborate {} {


#

# connection point bus_internal

#

add_interface bus_internal conduit end

set_interface_property bus_internal associatedClock clock_reset

set_interface_property bus_internal associatedReset clock_reset_reset

set_interface_property bus_internal ENABLED true

set_interface_property bus_internal EXPORT_OF ""

set_interface_property bus_internal PORT_NAME_MAP ""

set_interface_property bus_internal SVD_ADDRESS_GROUP ""


#LEDS interface

add_interface_port bus_internal frozen_avalon_monitor export Input 1


#

# connection point phy

#

add_interface phy conduit end

set_interface_property phy associatedClock clock_reset

set_interface_property phy associatedReset clock_reset_reset

set_interface_property phy ENABLED true

set_interface_property phy EXPORT_OF ""

set_interface_property phy PORT_NAME_MAP ""

set_interface_property phy SVD_ADDRESS_GROUP ""


#LEDS interface

add_interface_port phy F_LED0 export Output 1

add_interface_port phy F_LED1 export Output 1

add_interface_port phy F_LED2 export Output 1

add_interface_port phy F_LED3 export Output 1

add_interface_port phy F_LED4 export Output 1

add_interface_port phy F_LED5 export Output 1

add_interface_port phy F_LED6 export Output 1

add_interface_port phy F_LED7 export Output 1


set Processors [get_parameter_value NProcessors]

    for {set i 1} {$i <= $Processors} {incr i} {

        #

        # connection point s_processor$i for each processor defined

        #

        add_interface s_processor$i avalon end

        set_interface_property s_processor$i addressUnits WORDS

        set_interface_property s_processor$i associatedClock clock_reset

        set_interface_property s_processor$i associatedReset clock_reset_reset

        set_interface_property s_processor$i bitsPerSymbol 8

        set_interface_property s_processor$i burstOnBurstBoundariesOnly false

        set_interface_property s_processor$i burstcountUnits WORDS

        set_interface_property s_processor$i explicitAddressSpan 0

        set_interface_property s_processor$i holdTime 0

        set_interface_property s_processor$i linewrapBursts false

        set_interface_property s_processor$i maximumPendingReadTransactions 0

        set_interface_property s_processor$i readLatency 0

        set_interface_property s_processor$i readWaitStates 0

        set_interface_property s_processor$i readWaitTime 0

        set_interface_property s_processor$i setupTime 0

        set_interface_property s_processor$i timingUnits Cycles

        set_interface_property s_processor$i writeWaitTime 0

        set_interface_property s_processor$i ENABLED true


        add_interface_port s_processor$i slave_processor_address$i address Input 1

        add_interface_port s_processor$i slave_processor_read$i read Input 1

        add_interface_port s_processor$i slave_processor_write$i write Input 1

        add_interface_port s_processor$i slave_processor_readdata$i readdata Output 32

        add_interface_port s_processor$i slave_processor_writedata$i writedata Input 32

        # add_interface_port s_processor$i slave_processor_chipselect$i chipselect Input 1

        add_interface_port s_processor$i slave_processor_waitrequest$i waitrequest Output 1

        set_interface_assignment s_processor$i embeddedsw.configuration.isFlash 0

        set_interface_assignment s_processor$i embeddedsw.configuration.isMemoryDevice 0

        set_interface_assignment s_processor$i embeddedsw.configuration.isNonVolatileStorage 0

        set_interface_assignment s_processor$i embeddedsw.configuration.isPrintableDevice 0


        # ########################################## 01/09/2022

        #

        # connection point monitor for processors in grtos

        #

        add_interface s_processor_monitor$i avalon end

        set_interface_property s_processor_monitor$i addressUnits WORDS

        set_interface_property s_processor_monitor$i associatedClock clock_reset

        set_interface_property s_processor_monitor$i associatedReset clock_reset_reset

        set_interface_property s_processor_monitor$i bitsPerSymbol 8

        set_interface_property s_processor_monitor$i burstOnBurstBoundariesOnly false

        set_interface_property s_processor_monitor$i burstcountUnits WORDS

        set_interface_property s_processor_monitor$i explicitAddressSpan 0

        set_interface_property s_processor_monitor$i holdTime 0

        set_interface_property s_processor_monitor$i linewrapBursts false

        set_interface_property s_processor_monitor$i maximumPendingReadTransactions 0

        set_interface_property s_processor_monitor$i readLatency 0

        set_interface_property s_processor_monitor$i readWaitStates 0

        set_interface_property s_processor_monitor$i readWaitTime 0

        set_interface_property s_processor_monitor$i setupTime 0

        set_interface_property s_processor_monitor$i timingUnits Cycles

        set_interface_property s_processor_monitor$i writeWaitTime 0

        set_interface_property s_processor_monitor$i ENABLED true


        add_interface_port s_processor_monitor$i slave_processor_monitor_address$i address Input 3

        add_interface_port s_processor_monitor$i slave_processor_monitor_read$i read Input 1

        add_interface_port s_processor_monitor$i slave_processor_monitor_write$i write Input 1

        add_interface_port s_processor_monitor$i slave_processor_monitor_readdata$i readdata Output 32

        add_interface_port s_processor_monitor$i slave_processor_monitor_writedata$i writedata Input 32

        # add_interface_port s_processor_monitor$i slave_processor_chipselect$i chipselect Input 1

        add_interface_port s_processor_monitor$i slave_processor_monitor_waitrequest$i waitrequest Output 1

        set_interface_assignment s_processor_monitor$i embeddedsw.configuration.isFlash 0

        set_interface_assignment s_processor_monitor$i embeddedsw.configuration.isMemoryDevice 0

        set_interface_assignment s_processor_monitor$i embeddedsw.configuration.isNonVolatileStorage 0

        set_interface_assignment s_processor_monitor$i embeddedsw.configuration.isPrintableDevice 0


        # ########################################## 01/09/2022


        # ##########################################

        #

        # connection point slv_rst(1)

        #

        add_interface slv_rst$i reset start

        set_interface_property slv_rst$i associatedClock clock_reset

        # set_interface_property slv_rst$i associatedClock clk_out

        set_interface_property slv_rst$i associatedResetSinks clock_reset_reset

        set_interface_property slv_rst$i synchronousEdges DEASSERT

        # set_interface_property slv_rst$i synchronousEdges NONE

        # set_interface_property slv_rst$i synchronousEdges BOTH

        set_interface_property slv_rst$i ENABLED true


        add_interface_port slv_rst$i slave_rst$i reset Output 1

        # ##########################################

        #

        # connection point slv_irq(1)

        #

        add_interface slv_irq$i interrupt end

        set_interface_property slv_irq$i associatedAddressablePoint s_processor$i

        set_interface_property slv_irq$i associatedClock clock_reset

        set_interface_property slv_irq$i associatedReset clock_reset_reset

        set_interface_property slv_irq$i ENABLED true


        add_interface_port slv_irq$i slave_irq$i irq Output 1


    }


# #############################################

        #

        # connection point s_processor_monitor

        #

        add_interface s_processor_monitor avalon end

        set_interface_property s_processor_monitor addressUnits WORDS

        set_interface_property s_processor_monitor associatedClock clock_reset

        set_interface_property s_processor_monitor associatedReset clock_reset_reset

        set_interface_property s_processor_monitor bitsPerSymbol 8

        set_interface_property s_processor_monitor burstOnBurstBoundariesOnly false

        set_interface_property s_processor_monitor burstcountUnits WORDS

        set_interface_property s_processor_monitor explicitAddressSpan 0

        set_interface_property s_processor_monitor holdTime 0

        set_interface_property s_processor_monitor linewrapBursts false

        set_interface_property s_processor_monitor maximumPendingReadTransactions 0

        set_interface_property s_processor_monitor readLatency 0

        set_interface_property s_processor_monitor readWaitStates 0

        set_interface_property s_processor_monitor readWaitTime 0

        set_interface_property s_processor_monitor setupTime 0

        set_interface_property s_processor_monitor timingUnits Cycles

        set_interface_property s_processor_monitor writeWaitTime 0

        set_interface_property s_processor_monitor ENABLED true


        add_interface_port s_processor_monitor slave_processor_address_monitor address Input 8

        add_interface_port s_processor_monitor slave_processor_read_monitor read Input 1

        add_interface_port s_processor_monitor slave_processor_write_monitor write Input 1

        add_interface_port s_processor_monitor slave_processor_readdata_monitor readdata Output 32

        add_interface_port s_processor_monitor slave_processor_writedata_monitor writedata Input 32

        # add_interface_port s_processor_monitor slave_processor_chipselect_monitor chipselect Input 1

        add_interface_port s_processor_monitor slave_processor_waitrequest_monitor waitrequest Output 1

        set_interface_assignment s_processor_monitor embeddedsw.configuration.isFlash 0

        set_interface_assignment s_processor_monitor embeddedsw.configuration.isMemoryDevice 0

        set_interface_assignment s_processor_monitor embeddedsw.configuration.isNonVolatileStorage 0

        set_interface_assignment s_processor_monitor embeddedsw.configuration.isPrintableDevice 0

# #############################################


}