GeMRTOS
avalon_bridge.vhd
Go to the documentation of this file.
1 -- $Id: //avalon_bridge.vhd#1 $
2 -- $Revision: #1 $
3 -- $Date: 2017/03/06 $
4 -- $Author: Ricardo Cayssials $
5 -- --------------------------------------
6 library ieee;
7 use ieee.std_logic_1164.all;
8 use ieee.std_logic_unsigned.all;
9 use ieee.numeric_std.all;
10 
11 LIBRARY altera_mf;
12 USE altera_mf.all;
13 
14 
15 
16 entity avalon_bridge is
17 
18  generic
19  (
20  NProcessors : integer;
21  DATA_WIDTH : integer := 32;
22  ADDRESS_WIDTH : integer := 32;
23  BURSTCOUNT_WIDTH : integer := 1;
24  BYTEEN_WIDTH : integer := 4;
25  DEVICE_FAMILY : string
26  );
27 
28  port (
29  clk : in std_logic;
30  reset : in std_logic;
31 
32 
33  -- #####################################################################
34  -- Ports for avalon sniffer
35  -- #####################################################################
36  -- Processor 1
37  s1_waitrequest : out std_logic;
38  s1_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
39  s1_readdatavalid : out std_logic;
40  s1_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
41  s1_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
42  s1_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
43  s1_write : in std_logic;
44  s1_read : in std_logic;
45  s1_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
46  s1_debugaccess : in std_logic;
47  m1_waitrequest : in std_logic;
48  m1_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
49  m1_readdatavalid : in std_logic;
50  m1_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
51  m1_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
52  m1_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
53  m1_write : out std_logic;
54  m1_read : out std_logic;
55  m1_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
56  m1_debugaccess : out std_logic;
57  -- #####################################################################
58  -- Processor 2
59  s2_waitrequest : out std_logic;
60  s2_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
61  s2_readdatavalid : out std_logic;
62  s2_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
63  s2_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
64  s2_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
65  s2_write : in std_logic;
66  s2_read : in std_logic;
67  s2_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
68  s2_debugaccess : in std_logic;
69  m2_waitrequest : in std_logic;
70  m2_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
71  m2_readdatavalid : in std_logic;
72  m2_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
73  m2_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
74  m2_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
75  m2_write : out std_logic;
76  m2_read : out std_logic;
77  m2_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
78  m2_debugaccess : out std_logic;
79  -- #####################################################################
80  -- Processor 3
81  s3_waitrequest : out std_logic;
82  s3_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
83  s3_readdatavalid : out std_logic;
84  s3_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
85  s3_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
86  s3_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
87  s3_write : in std_logic;
88  s3_read : in std_logic;
89  s3_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
90  s3_debugaccess : in std_logic;
91  m3_waitrequest : in std_logic;
92  m3_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
93  m3_readdatavalid : in std_logic;
94  m3_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
95  m3_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
96  m3_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
97  m3_write : out std_logic;
98  m3_read : out std_logic;
99  m3_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
100  m3_debugaccess : out std_logic;
101  -- #####################################################################
102  -- Processor 4
103  s4_waitrequest : out std_logic;
104  s4_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
105  s4_readdatavalid : out std_logic;
106  s4_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
107  s4_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
108  s4_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
109  s4_write : in std_logic;
110  s4_read : in std_logic;
111  s4_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
112  s4_debugaccess : in std_logic;
113  m4_waitrequest : in std_logic;
114  m4_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
115  m4_readdatavalid : in std_logic;
116  m4_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
117  m4_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
118  m4_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
119  m4_write : out std_logic;
120  m4_read : out std_logic;
121  m4_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
122  m4_debugaccess : out std_logic;
123  -- #####################################################################
124  -- Processor 5
125  s5_waitrequest : out std_logic;
126  s5_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
127  s5_readdatavalid : out std_logic;
128  s5_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
129  s5_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
130  s5_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
131  s5_write : in std_logic;
132  s5_read : in std_logic;
133  s5_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
134  s5_debugaccess : in std_logic;
135  m5_waitrequest : in std_logic;
136  m5_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
137  m5_readdatavalid : in std_logic;
138  m5_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
139  m5_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
140  m5_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
141  m5_write : out std_logic;
142  m5_read : out std_logic;
143  m5_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
144  m5_debugaccess : out std_logic;
145  -- #####################################################################
146  -- Processor 6
147  s6_waitrequest : out std_logic;
148  s6_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
149  s6_readdatavalid : out std_logic;
150  s6_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
151  s6_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
152  s6_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
153  s6_write : in std_logic;
154  s6_read : in std_logic;
155  s6_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
156  s6_debugaccess : in std_logic;
157  m6_waitrequest : in std_logic;
158  m6_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
159  m6_readdatavalid : in std_logic;
160  m6_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
161  m6_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
162  m6_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
163  m6_write : out std_logic;
164  m6_read : out std_logic;
165  m6_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
166  m6_debugaccess : out std_logic;
167  -- #####################################################################
168  -- Processor 7
169  s7_waitrequest : out std_logic;
170  s7_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
171  s7_readdatavalid : out std_logic;
172  s7_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
173  s7_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
174  s7_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
175  s7_write : in std_logic;
176  s7_read : in std_logic;
177  s7_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
178  s7_debugaccess : in std_logic;
179  m7_waitrequest : in std_logic;
180  m7_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
181  m7_readdatavalid : in std_logic;
182  m7_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
183  m7_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
184  m7_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
185  m7_write : out std_logic;
186  m7_read : out std_logic;
187  m7_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
188  m7_debugaccess : out std_logic;
189  -- #####################################################################
190  -- Processor 8
191  s8_waitrequest : out std_logic;
192  s8_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
193  s8_readdatavalid : out std_logic;
194  s8_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
195  s8_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
196  s8_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
197  s8_write : in std_logic;
198  s8_read : in std_logic;
199  s8_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
200  s8_debugaccess : in std_logic;
201  m8_waitrequest : in std_logic;
202  m8_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
203  m8_readdatavalid : in std_logic;
204  m8_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
205  m8_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
206  m8_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
207  m8_write : out std_logic;
208  m8_read : out std_logic;
209  m8_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
210  m8_debugaccess : out std_logic;
211  -- #####################################################################
212  -- Processor 9
213  s9_waitrequest : out std_logic;
214  s9_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
215  s9_readdatavalid : out std_logic;
216  s9_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
217  s9_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
218  s9_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
219  s9_write : in std_logic;
220  s9_read : in std_logic;
221  s9_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
222  s9_debugaccess : in std_logic;
223  m9_waitrequest : in std_logic;
224  m9_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
225  m9_readdatavalid : in std_logic;
226  m9_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
227  m9_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
228  m9_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
229  m9_write : out std_logic;
230  m9_read : out std_logic;
231  m9_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
232  m9_debugaccess : out std_logic;
233  -- #####################################################################
234  -- Processor 10
235  s10_waitrequest : out std_logic;
236  s10_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
237  s10_readdatavalid : out std_logic;
238  s10_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
239  s10_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
240  s10_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
241  s10_write : in std_logic;
242  s10_read : in std_logic;
243  s10_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
244  s10_debugaccess : in std_logic;
245  m10_waitrequest : in std_logic;
246  m10_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
247  m10_readdatavalid : in std_logic;
248  m10_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
249  m10_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
250  m10_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
251  m10_write : out std_logic;
252  m10_read : out std_logic;
253  m10_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
254  m10_debugaccess : out std_logic;
255  -- #####################################################################
256  -- Processor 11
257  s11_waitrequest : out std_logic;
258  s11_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
259  s11_readdatavalid : out std_logic;
260  s11_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
261  s11_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
262  s11_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
263  s11_write : in std_logic;
264  s11_read : in std_logic;
265  s11_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
266  s11_debugaccess : in std_logic;
267  m11_waitrequest : in std_logic;
268  m11_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
269  m11_readdatavalid : in std_logic;
270  m11_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
271  m11_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
272  m11_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
273  m11_write : out std_logic;
274  m11_read : out std_logic;
275  m11_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
276  m11_debugaccess : out std_logic;
277  -- #####################################################################
278  -- Processor 12
279  s12_waitrequest : out std_logic;
280  s12_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
281  s12_readdatavalid : out std_logic;
282  s12_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
283  s12_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
284  s12_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
285  s12_write : in std_logic;
286  s12_read : in std_logic;
287  s12_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
288  s12_debugaccess : in std_logic;
289  m12_waitrequest : in std_logic;
290  m12_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
291  m12_readdatavalid : in std_logic;
292  m12_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
293  m12_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
294  m12_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
295  m12_write : out std_logic;
296  m12_read : out std_logic;
297  m12_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
298  m12_debugaccess : out std_logic;
299  -- #####################################################################
300  -- Processor 13
301  s13_waitrequest : out std_logic;
302  s13_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
303  s13_readdatavalid : out std_logic;
304  s13_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
305  s13_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
306  s13_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
307  s13_write : in std_logic;
308  s13_read : in std_logic;
309  s13_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
310  s13_debugaccess : in std_logic;
311  m13_waitrequest : in std_logic;
312  m13_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
313  m13_readdatavalid : in std_logic;
314  m13_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
315  m13_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
316  m13_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
317  m13_write : out std_logic;
318  m13_read : out std_logic;
319  m13_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
320  m13_debugaccess : out std_logic;
321  -- #####################################################################
322  -- Processor 13
323  s14_waitrequest : out std_logic;
324  s14_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
325  s14_readdatavalid : out std_logic;
326  s14_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
327  s14_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
328  s14_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
329  s14_write : in std_logic;
330  s14_read : in std_logic;
331  s14_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
332  s14_debugaccess : in std_logic;
333  m14_waitrequest : in std_logic;
334  m14_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
335  m14_readdatavalid : in std_logic;
336  m14_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
337  m14_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
338  m14_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
339  m14_write : out std_logic;
340  m14_read : out std_logic;
341  m14_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
342  m14_debugaccess : out std_logic;
343  -- #####################################################################
344  -- Processor 14
345  s15_waitrequest : out std_logic;
346  s15_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
347  s15_readdatavalid : out std_logic;
348  s15_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
349  s15_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
350  s15_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
351  s15_write : in std_logic;
352  s15_read : in std_logic;
353  s15_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
354  s15_debugaccess : in std_logic;
355  m15_waitrequest : in std_logic;
356  m15_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
357  m15_readdatavalid : in std_logic;
358  m15_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
359  m15_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
360  m15_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
361  m15_write : out std_logic;
362  m15_read : out std_logic;
363  m15_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
364  m15_debugaccess : out std_logic;
365  -- #####################################################################
366  -- Processor 16
367  s16_waitrequest : out std_logic;
368  s16_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
369  s16_readdatavalid : out std_logic;
370  s16_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
371  s16_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
372  s16_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
373  s16_write : in std_logic;
374  s16_read : in std_logic;
375  s16_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
376  s16_debugaccess : in std_logic;
377  m16_waitrequest : in std_logic;
378  m16_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
379  m16_readdatavalid : in std_logic;
380  m16_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
381  m16_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
382  m16_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
383  m16_write : out std_logic;
384  m16_read : out std_logic;
385  m16_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
386  m16_debugaccess : out std_logic;
387  -- #####################################################################
388  -- Processor 17
389  s17_waitrequest : out std_logic;
390  s17_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
391  s17_readdatavalid : out std_logic;
392  s17_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
393  s17_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
394  s17_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
395  s17_write : in std_logic;
396  s17_read : in std_logic;
397  s17_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
398  s17_debugaccess : in std_logic;
399  m17_waitrequest : in std_logic;
400  m17_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
401  m17_readdatavalid : in std_logic;
402  m17_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
403  m17_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
404  m17_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
405  m17_write : out std_logic;
406  m17_read : out std_logic;
407  m17_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
408  m17_debugaccess : out std_logic;
409  -- #####################################################################
410  -- Processor 18
411  s18_waitrequest : out std_logic;
412  s18_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
413  s18_readdatavalid : out std_logic;
414  s18_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
415  s18_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
416  s18_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
417  s18_write : in std_logic;
418  s18_read : in std_logic;
419  s18_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
420  s18_debugaccess : in std_logic;
421  m18_waitrequest : in std_logic;
422  m18_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
423  m18_readdatavalid : in std_logic;
424  m18_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
425  m18_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
426  m18_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
427  m18_write : out std_logic;
428  m18_read : out std_logic;
429  m18_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
430  m18_debugaccess : out std_logic;
431  -- #####################################################################
432  -- Processor 19
433  s19_waitrequest : out std_logic;
434  s19_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
435  s19_readdatavalid : out std_logic;
436  s19_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
437  s19_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
438  s19_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
439  s19_write : in std_logic;
440  s19_read : in std_logic;
441  s19_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
442  s19_debugaccess : in std_logic;
443  m19_waitrequest : in std_logic;
444  m19_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
445  m19_readdatavalid : in std_logic;
446  m19_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
447  m19_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
448  m19_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
449  m19_write : out std_logic;
450  m19_read : out std_logic;
451  m19_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
452  m19_debugaccess : out std_logic;
453  -- #####################################################################
454  -- Processor 20
455  s20_waitrequest : out std_logic;
456  s20_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
457  s20_readdatavalid : out std_logic;
458  s20_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
459  s20_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
460  s20_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
461  s20_write : in std_logic;
462  s20_read : in std_logic;
463  s20_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
464  s20_debugaccess : in std_logic;
465  m20_waitrequest : in std_logic;
466  m20_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
467  m20_readdatavalid : in std_logic;
468  m20_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
469  m20_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
470  m20_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
471  m20_write : out std_logic;
472  m20_read : out std_logic;
473  m20_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
474  m20_debugaccess : out std_logic;
475  -- #####################################################################
476  -- Processor 21
477  s21_waitrequest : out std_logic;
478  s21_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
479  s21_readdatavalid : out std_logic;
480  s21_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
481  s21_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
482  s21_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
483  s21_write : in std_logic;
484  s21_read : in std_logic;
485  s21_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
486  s21_debugaccess : in std_logic;
487  m21_waitrequest : in std_logic;
488  m21_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
489  m21_readdatavalid : in std_logic;
490  m21_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
491  m21_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
492  m21_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
493  m21_write : out std_logic;
494  m21_read : out std_logic;
495  m21_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
496  m21_debugaccess : out std_logic;
497  -- #####################################################################
498  -- Processor 22
499  s22_waitrequest : out std_logic;
500  s22_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
501  s22_readdatavalid : out std_logic;
502  s22_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
503  s22_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
504  s22_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
505  s22_write : in std_logic;
506  s22_read : in std_logic;
507  s22_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
508  s22_debugaccess : in std_logic;
509  m22_waitrequest : in std_logic;
510  m22_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
511  m22_readdatavalid : in std_logic;
512  m22_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
513  m22_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
514  m22_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
515  m22_write : out std_logic;
516  m22_read : out std_logic;
517  m22_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
518  m22_debugaccess : out std_logic;
519  -- #####################################################################
520  -- Processor 23
521  s23_waitrequest : out std_logic;
522  s23_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
523  s23_readdatavalid : out std_logic;
524  s23_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
525  s23_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
526  s23_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
527  s23_write : in std_logic;
528  s23_read : in std_logic;
529  s23_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
530  s23_debugaccess : in std_logic;
531  m23_waitrequest : in std_logic;
532  m23_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
533  m23_readdatavalid : in std_logic;
534  m23_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
535  m23_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
536  m23_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
537  m23_write : out std_logic;
538  m23_read : out std_logic;
539  m23_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
540  m23_debugaccess : out std_logic;
541  -- #####################################################################
542  -- Processor 24
543  s24_waitrequest : out std_logic;
544  s24_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
545  s24_readdatavalid : out std_logic;
546  s24_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
547  s24_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
548  s24_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
549  s24_write : in std_logic;
550  s24_read : in std_logic;
551  s24_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
552  s24_debugaccess : in std_logic;
553  m24_waitrequest : in std_logic;
554  m24_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
555  m24_readdatavalid : in std_logic;
556  m24_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
557  m24_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
558  m24_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
559  m24_write : out std_logic;
560  m24_read : out std_logic;
561  m24_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
562  m24_debugaccess : out std_logic;
563  -- #####################################################################
564  -- Processor 25
565  s25_waitrequest : out std_logic;
566  s25_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
567  s25_readdatavalid : out std_logic;
568  s25_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
569  s25_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
570  s25_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
571  s25_write : in std_logic;
572  s25_read : in std_logic;
573  s25_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
574  s25_debugaccess : in std_logic;
575  m25_waitrequest : in std_logic;
576  m25_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
577  m25_readdatavalid : in std_logic;
578  m25_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
579  m25_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
580  m25_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
581  m25_write : out std_logic;
582  m25_read : out std_logic;
583  m25_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
584  m25_debugaccess : out std_logic;
585  -- #####################################################################
586  -- Processor 26
587  s26_waitrequest : out std_logic;
588  s26_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
589  s26_readdatavalid : out std_logic;
590  s26_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
591  s26_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
592  s26_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
593  s26_write : in std_logic;
594  s26_read : in std_logic;
595  s26_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
596  s26_debugaccess : in std_logic;
597  m26_waitrequest : in std_logic;
598  m26_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
599  m26_readdatavalid : in std_logic;
600  m26_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
601  m26_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
602  m26_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
603  m26_write : out std_logic;
604  m26_read : out std_logic;
605  m26_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
606  m26_debugaccess : out std_logic;
607  -- #####################################################################
608  -- Processor 27
609  s27_waitrequest : out std_logic;
610  s27_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
611  s27_readdatavalid : out std_logic;
612  s27_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
613  s27_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
614  s27_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
615  s27_write : in std_logic;
616  s27_read : in std_logic;
617  s27_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
618  s27_debugaccess : in std_logic;
619  m27_waitrequest : in std_logic;
620  m27_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
621  m27_readdatavalid : in std_logic;
622  m27_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
623  m27_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
624  m27_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
625  m27_write : out std_logic;
626  m27_read : out std_logic;
627  m27_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
628  m27_debugaccess : out std_logic;
629  -- #####################################################################
630  -- Processor 28
631  s28_waitrequest : out std_logic;
632  s28_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
633  s28_readdatavalid : out std_logic;
634  s28_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
635  s28_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
636  s28_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
637  s28_write : in std_logic;
638  s28_read : in std_logic;
639  s28_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
640  s28_debugaccess : in std_logic;
641  m28_waitrequest : in std_logic;
642  m28_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
643  m28_readdatavalid : in std_logic;
644  m28_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
645  m28_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
646  m28_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
647  m28_write : out std_logic;
648  m28_read : out std_logic;
649  m28_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
650  m28_debugaccess : out std_logic;
651  -- #####################################################################
652  -- Processor 29
653  s29_waitrequest : out std_logic;
654  s29_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
655  s29_readdatavalid : out std_logic;
656  s29_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
657  s29_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
658  s29_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
659  s29_write : in std_logic;
660  s29_read : in std_logic;
661  s29_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
662  s29_debugaccess : in std_logic;
663  m29_waitrequest : in std_logic;
664  m29_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
665  m29_readdatavalid : in std_logic;
666  m29_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
667  m29_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
668  m29_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
669  m29_write : out std_logic;
670  m29_read : out std_logic;
671  m29_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
672  m29_debugaccess : out std_logic;
673  -- #####################################################################
674  -- Processor 30
675  s30_waitrequest : out std_logic;
676  s30_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
677  s30_readdatavalid : out std_logic;
678  s30_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
679  s30_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
680  s30_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
681  s30_write : in std_logic;
682  s30_read : in std_logic;
683  s30_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
684  s30_debugaccess : in std_logic;
685  m30_waitrequest : in std_logic;
686  m30_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
687  m30_readdatavalid : in std_logic;
688  m30_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
689  m30_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
690  m30_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
691  m30_write : out std_logic;
692  m30_read : out std_logic;
693  m30_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
694  m30_debugaccess : out std_logic;
695  -- #####################################################################
696  -- Processor 31
697  s31_waitrequest : out std_logic;
698  s31_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
699  s31_readdatavalid : out std_logic;
700  s31_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
701  s31_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
702  s31_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
703  s31_write : in std_logic;
704  s31_read : in std_logic;
705  s31_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
706  s31_debugaccess : in std_logic;
707  m31_waitrequest : in std_logic;
708  m31_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
709  m31_readdatavalid : in std_logic;
710  m31_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
711  m31_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
712  m31_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
713  m31_write : out std_logic;
714  m31_read : out std_logic;
715  m31_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
716  m31_debugaccess : out std_logic;
717  -- #####################################################################
718  -- Processor 32
719  s32_waitrequest : out std_logic;
720  s32_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
721  s32_readdatavalid : out std_logic;
722  s32_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
723  s32_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
724  s32_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
725  s32_write : in std_logic;
726  s32_read : in std_logic;
727  s32_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
728  s32_debugaccess : in std_logic;
729  m32_waitrequest : in std_logic;
730  m32_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
731  m32_readdatavalid : in std_logic;
732  m32_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
733  m32_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
734  m32_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
735  m32_write : out std_logic;
736  m32_read : out std_logic;
737  m32_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
738  m32_debugaccess : out std_logic
739 
740  );
741 
742 end entity avalon_bridge;
743 
744 architecture AM1 of avalon_bridge is
745 
746 
747 begin
748 
749  m1_burstcount <= s1_burstcount;
750  m1_writedata <= s1_writedata;
751  m1_address <= s1_address;
752  m1_write <= s1_write;
753  m1_read <= s1_read;
754  m1_byteenable <= s1_byteenable;
755  m1_debugaccess <= s1_debugaccess;
756  s1_waitrequest <= m1_waitrequest;
757  s1_readdatavalid <= m1_readdatavalid;
758  s1_readdata <= m1_readdata;
759 
760  m2_burstcount <= s2_burstcount;
761  m2_writedata <= s2_writedata;
762  m2_address <= s2_address;
763  m2_write <= s2_write;
764  m2_read <= s2_read;
765  m2_byteenable <= s2_byteenable;
766  m2_debugaccess <= s2_debugaccess;
767  s2_waitrequest <= m2_waitrequest;
768  s2_readdatavalid <= m2_readdatavalid;
769  s2_readdata <= m2_readdata;
770 
771  m3_burstcount <= s3_burstcount;
772  m3_writedata <= s3_writedata;
773  m3_address <= s3_address;
774  m3_write <= s3_write;
775  m3_read <= s3_read;
776  m3_byteenable <= s3_byteenable;
777  m3_debugaccess <= s3_debugaccess;
778  s3_waitrequest <= m3_waitrequest;
779  s3_readdatavalid <= m3_readdatavalid;
780  s3_readdata <= m3_readdata;
781 
782  m4_burstcount <= s4_burstcount;
783  m4_writedata <= s4_writedata;
784  m4_address <= s4_address;
785  m4_write <= s4_write;
786  m4_read <= s4_read;
787  m4_byteenable <= s4_byteenable;
788  m4_debugaccess <= s4_debugaccess;
789  s4_waitrequest <= m4_waitrequest;
790  s4_readdatavalid <= m4_readdatavalid;
791  s4_readdata <= m4_readdata;
792 
793  m5_burstcount <= s5_burstcount;
794  m5_writedata <= s5_writedata;
795  m5_address <= s5_address;
796  m5_write <= s5_write;
797  m5_read <= s5_read;
798  m5_byteenable <= s5_byteenable;
799  m5_debugaccess <= s5_debugaccess;
800  s5_waitrequest <= m5_waitrequest;
801  s5_readdatavalid <= m5_readdatavalid;
802  s5_readdata <= m5_readdata;
803 
804  m6_burstcount <= s6_burstcount;
805  m6_writedata <= s6_writedata;
806  m6_address <= s6_address;
807  m6_write <= s6_write;
808  m6_read <= s6_read;
809  m6_byteenable <= s6_byteenable;
810  m6_debugaccess <= s6_debugaccess;
811  s6_waitrequest <= m6_waitrequest;
812  s6_readdatavalid <= m6_readdatavalid;
813  s6_readdata <= m6_readdata;
814 
815  m7_burstcount <= s7_burstcount;
816  m7_writedata <= s7_writedata;
817  m7_address <= s7_address;
818  m7_write <= s7_write;
819  m7_read <= s7_read;
820  m7_byteenable <= s7_byteenable;
821  m7_debugaccess <= s7_debugaccess;
822  s7_waitrequest <= m7_waitrequest;
823  s7_readdatavalid <= m7_readdatavalid;
824  s7_readdata <= m7_readdata;
825 
826  m8_burstcount <= s8_burstcount;
827  m8_writedata <= s8_writedata;
828  m8_address <= s8_address;
829  m8_write <= s8_write;
830  m8_read <= s8_read;
831  m8_byteenable <= s8_byteenable;
832  m8_debugaccess <= s8_debugaccess;
833  s8_waitrequest <= m8_waitrequest;
834  s8_readdatavalid <= m8_readdatavalid;
835  s8_readdata <= m8_readdata;
836 
837  m9_burstcount <= s9_burstcount;
838  m9_writedata <= s9_writedata;
839  m9_address <= s9_address;
840  m9_write <= s9_write;
841  m9_read <= s9_read;
842  m9_byteenable <= s9_byteenable;
843  m9_debugaccess <= s9_debugaccess;
844  s9_waitrequest <= m9_waitrequest;
845  s9_readdatavalid <= m9_readdatavalid;
846  s9_readdata <= m9_readdata;
847 
848  m10_burstcount <= s10_burstcount;
849  m10_writedata <= s10_writedata;
850  m10_address <= s10_address;
851  m10_write <= s10_write;
852  m10_read <= s10_read;
853  m10_byteenable <= s10_byteenable;
854  m10_debugaccess <= s10_debugaccess;
855  s10_waitrequest <= m10_waitrequest;
856  s10_readdatavalid <= m10_readdatavalid;
857  s10_readdata <= m10_readdata;
858 
859  m11_burstcount <= s11_burstcount;
860  m11_writedata <= s11_writedata;
861  m11_address <= s11_address;
862  m11_write <= s11_write;
863  m11_read <= s11_read;
864  m11_byteenable <= s11_byteenable;
865  m11_debugaccess <= s11_debugaccess;
866  s11_waitrequest <= m11_waitrequest;
867  s11_readdatavalid <= m11_readdatavalid;
868  s11_readdata <= m11_readdata;
869 
870  m12_burstcount <= s12_burstcount;
871  m12_writedata <= s12_writedata;
872  m12_address <= s12_address;
873  m12_write <= s12_write;
874  m12_read <= s12_read;
875  m12_byteenable <= s12_byteenable;
876  m12_debugaccess <= s12_debugaccess;
877  s12_waitrequest <= m12_waitrequest;
878  s12_readdatavalid <= m12_readdatavalid;
879  s12_readdata <= m12_readdata;
880 
881  m13_burstcount <= s13_burstcount;
882  m13_writedata <= s13_writedata;
883  m13_address <= s13_address;
884  m13_write <= s13_write;
885  m13_read <= s13_read;
886  m13_byteenable <= s13_byteenable;
887  m13_debugaccess <= s13_debugaccess;
888  s13_waitrequest <= m13_waitrequest;
889  s13_readdatavalid <= m13_readdatavalid;
890  s13_readdata <= m13_readdata;
891 
892  m14_burstcount <= s14_burstcount;
893  m14_writedata <= s14_writedata;
894  m14_address <= s14_address;
895  m14_write <= s14_write;
896  m14_read <= s14_read;
897  m14_byteenable <= s14_byteenable;
898  m14_debugaccess <= s14_debugaccess;
899  s14_waitrequest <= m14_waitrequest;
900  s14_readdatavalid <= m14_readdatavalid;
901  s14_readdata <= m14_readdata;
902 
903  m15_burstcount <= s15_burstcount;
904  m15_writedata <= s15_writedata;
905  m15_address <= s15_address;
906  m15_write <= s15_write;
907  m15_read <= s15_read;
908  m15_byteenable <= s15_byteenable;
909  m15_debugaccess <= s15_debugaccess;
910  s15_waitrequest <= m15_waitrequest;
911  s15_readdatavalid <= m15_readdatavalid;
912  s15_readdata <= m15_readdata;
913 
914  m16_burstcount <= s16_burstcount;
915  m16_writedata <= s16_writedata;
916  m16_address <= s16_address;
917  m16_write <= s16_write;
918  m16_read <= s16_read;
919  m16_byteenable <= s16_byteenable;
920  m16_debugaccess <= s16_debugaccess;
921  s16_waitrequest <= m16_waitrequest;
922  s16_readdatavalid <= m16_readdatavalid;
923  s16_readdata <= m16_readdata;
924 
925  m17_burstcount <= s17_burstcount;
926  m17_writedata <= s17_writedata;
927  m17_address <= s17_address;
928  m17_write <= s17_write;
929  m17_read <= s17_read;
930  m17_byteenable <= s17_byteenable;
931  m17_debugaccess <= s17_debugaccess;
932  s17_waitrequest <= m17_waitrequest;
933  s17_readdatavalid <= m17_readdatavalid;
934  s17_readdata <= m17_readdata;
935 
936  m18_burstcount <= s18_burstcount;
937  m18_writedata <= s18_writedata;
938  m18_address <= s18_address;
939  m18_write <= s18_write;
940  m18_read <= s18_read;
941  m18_byteenable <= s18_byteenable;
942  m18_debugaccess <= s18_debugaccess;
943  s18_waitrequest <= m18_waitrequest;
944  s18_readdatavalid <= m18_readdatavalid;
945  s18_readdata <= m18_readdata;
946 
947  m19_burstcount <= s19_burstcount;
948  m19_writedata <= s19_writedata;
949  m19_address <= s19_address;
950  m19_write <= s19_write;
951  m19_read <= s19_read;
952  m19_byteenable <= s19_byteenable;
953  m19_debugaccess <= s19_debugaccess;
954  s19_waitrequest <= m19_waitrequest;
955  s19_readdatavalid <= m19_readdatavalid;
956  s19_readdata <= m19_readdata;
957 
958  m20_burstcount <= s20_burstcount;
959  m20_writedata <= s20_writedata;
960  m20_address <= s20_address;
961  m20_write <= s20_write;
962  m20_read <= s20_read;
963  m20_byteenable <= s20_byteenable;
964  m20_debugaccess <= s20_debugaccess;
965  s20_waitrequest <= m20_waitrequest;
966  s20_readdatavalid <= m20_readdatavalid;
967  s20_readdata <= m20_readdata;
968 
969  m21_burstcount <= s21_burstcount;
970  m21_writedata <= s21_writedata;
971  m21_address <= s21_address;
972  m21_write <= s21_write;
973  m21_read <= s21_read;
974  m21_byteenable <= s21_byteenable;
975  m21_debugaccess <= s21_debugaccess;
976  s21_waitrequest <= m21_waitrequest;
977  s21_readdatavalid <= m21_readdatavalid;
978  s21_readdata <= m21_readdata;
979 
980  m22_burstcount <= s22_burstcount;
981  m22_writedata <= s22_writedata;
982  m22_address <= s22_address;
983  m22_write <= s22_write;
984  m22_read <= s22_read;
985  m22_byteenable <= s22_byteenable;
986  m22_debugaccess <= s22_debugaccess;
987  s22_waitrequest <= m22_waitrequest;
988  s22_readdatavalid <= m22_readdatavalid;
989  s22_readdata <= m22_readdata;
990 
991  m23_burstcount <= s23_burstcount;
992  m23_writedata <= s23_writedata;
993  m23_address <= s23_address;
994  m23_write <= s23_write;
995  m23_read <= s23_read;
996  m23_byteenable <= s23_byteenable;
997  m23_debugaccess <= s23_debugaccess;
998  s23_waitrequest <= m23_waitrequest;
999  s23_readdatavalid <= m23_readdatavalid;
1000  s23_readdata <= m23_readdata;
1001 
1002  m24_burstcount <= s24_burstcount;
1003  m24_writedata <= s24_writedata;
1004  m24_address <= s24_address;
1005  m24_write <= s24_write;
1006  m24_read <= s24_read;
1007  m24_byteenable <= s24_byteenable;
1008  m24_debugaccess <= s24_debugaccess;
1009  s24_waitrequest <= m24_waitrequest;
1010  s24_readdatavalid <= m24_readdatavalid;
1011  s24_readdata <= m24_readdata;
1012 
1013  m25_burstcount <= s25_burstcount;
1014  m25_writedata <= s25_writedata;
1015  m25_address <= s25_address;
1016  m25_write <= s25_write;
1017  m25_read <= s25_read;
1018  m25_byteenable <= s25_byteenable;
1019  m25_debugaccess <= s25_debugaccess;
1020  s25_waitrequest <= m25_waitrequest;
1021  s25_readdatavalid <= m25_readdatavalid;
1022  s25_readdata <= m25_readdata;
1023 
1024  m26_burstcount <= s26_burstcount;
1025  m26_writedata <= s26_writedata;
1026  m26_address <= s26_address;
1027  m26_write <= s26_write;
1028  m26_read <= s26_read;
1029  m26_byteenable <= s26_byteenable;
1030  m26_debugaccess <= s26_debugaccess;
1031  s26_waitrequest <= m26_waitrequest;
1032  s26_readdatavalid <= m26_readdatavalid;
1033  s26_readdata <= m26_readdata;
1034 
1035  m27_burstcount <= s27_burstcount;
1036  m27_writedata <= s27_writedata;
1037  m27_address <= s27_address;
1038  m27_write <= s27_write;
1039  m27_read <= s27_read;
1040  m27_byteenable <= s27_byteenable;
1041  m27_debugaccess <= s27_debugaccess;
1042  s27_waitrequest <= m27_waitrequest;
1043  s27_readdatavalid <= m27_readdatavalid;
1044  s27_readdata <= m27_readdata;
1045 
1046  m28_burstcount <= s28_burstcount;
1047  m28_writedata <= s28_writedata;
1048  m28_address <= s28_address;
1049  m28_write <= s28_write;
1050  m28_read <= s28_read;
1051  m28_byteenable <= s28_byteenable;
1052  m28_debugaccess <= s28_debugaccess;
1053  s28_waitrequest <= m28_waitrequest;
1054  s28_readdatavalid <= m28_readdatavalid;
1055  s28_readdata <= m28_readdata;
1056 
1057  m29_burstcount <= s29_burstcount;
1058  m29_writedata <= s29_writedata;
1059  m29_address <= s29_address;
1060  m29_write <= s29_write;
1061  m29_read <= s29_read;
1062  m29_byteenable <= s29_byteenable;
1063  m29_debugaccess <= s29_debugaccess;
1064  s29_waitrequest <= m29_waitrequest;
1065  s29_readdatavalid <= m29_readdatavalid;
1066  s29_readdata <= m29_readdata;
1067 
1068  m30_burstcount <= s30_burstcount;
1069  m30_writedata <= s30_writedata;
1070  m30_address <= s30_address;
1071  m30_write <= s30_write;
1072  m30_read <= s30_read;
1073  m30_byteenable <= s30_byteenable;
1074  m30_debugaccess <= s30_debugaccess;
1075  s30_waitrequest <= m30_waitrequest;
1076  s30_readdatavalid <= m30_readdatavalid;
1077  s30_readdata <= m30_readdata;
1078 
1079  m31_burstcount <= s31_burstcount;
1080  m31_writedata <= s31_writedata;
1081  m31_address <= s31_address;
1082  m31_write <= s31_write;
1083  m31_read <= s31_read;
1084  m31_byteenable <= s31_byteenable;
1085  m31_debugaccess <= s31_debugaccess;
1086  s31_waitrequest <= m31_waitrequest;
1087  s31_readdatavalid <= m31_readdatavalid;
1088  s31_readdata <= m31_readdata;
1089 
1090  m32_burstcount <= s32_burstcount;
1091  m32_writedata <= s32_writedata;
1092  m32_address <= s32_address;
1093  m32_write <= s32_write;
1094  m32_read <= s32_read;
1095  m32_byteenable <= s32_byteenable;
1096  m32_debugaccess <= s32_debugaccess;
1097  s32_waitrequest <= m32_waitrequest;
1098  s32_readdatavalid <= m32_readdatavalid;
1099  s32_readdata <= m32_readdata;
1100 
1101 end architecture AM1;
avalon_bridge.s18_write
in s18_writestd_logic
Definition: avalon_bridge.vhd:417
avalon_bridge.s17_readdatavalid
out s17_readdatavalidstd_logic
Definition: avalon_bridge.vhd:391
avalon_bridge.m12_burstcount
out m12_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:292
avalon_bridge.NProcessors
NProcessorsinteger
Definition: avalon_bridge.vhd:20
avalon_bridge.BURSTCOUNT_WIDTH
BURSTCOUNT_WIDTHinteger := 1
Definition: avalon_bridge.vhd:23
avalon_bridge.s5_read
in s5_readstd_logic
Definition: avalon_bridge.vhd:132
avalon_bridge.m25_write
out m25_writestd_logic
Definition: avalon_bridge.vhd:581
avalon_bridge.s6_debugaccess
in s6_debugaccessstd_logic
Definition: avalon_bridge.vhd:156
avalon_bridge.s29_writedata
in s29_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:657
avalon_bridge.m1_read
out m1_readstd_logic
Definition: avalon_bridge.vhd:54
avalon_bridge.s12_read
in s12_readstd_logic
Definition: avalon_bridge.vhd:286
avalon_bridge.s21_readdata
out s21_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:478
avalon_bridge.m22_address
out m22_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:514
avalon_bridge.m29_byteenable
out m29_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:671
avalon_bridge.s27_debugaccess
in s27_debugaccessstd_logic
Definition: avalon_bridge.vhd:618
avalon_bridge.m12_write
out m12_writestd_logic
Definition: avalon_bridge.vhd:295
avalon_bridge.s12_writedata
in s12_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:283
avalon_bridge.s21_burstcount
in s21_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:480
avalon_bridge.m31_address
out m31_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:712
avalon_bridge.m13_address
out m13_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:316
avalon_bridge.s29_waitrequest
out s29_waitrequeststd_logic
Definition: avalon_bridge.vhd:653
avalon_bridge.s11_readdatavalid
out s11_readdatavalidstd_logic
Definition: avalon_bridge.vhd:259
avalon_bridge.m19_byteenable
out m19_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:451
avalon_bridge.s1_readdatavalid
out s1_readdatavalidstd_logic
Definition: avalon_bridge.vhd:39
avalon_bridge.s16_writedata
in s16_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:371
avalon_bridge.m5_address
out m5_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:140
avalon_bridge.m19_waitrequest
in m19_waitrequeststd_logic
Definition: avalon_bridge.vhd:443
avalon_bridge.m23_byteenable
out m23_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:539
avalon_bridge.m17_burstcount
out m17_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:402
avalon_bridge.m3_address
out m3_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:96
avalon_bridge.s32_read
in s32_readstd_logic
Definition: avalon_bridge.vhd:726
avalon_bridge.m9_byteenable
out m9_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:231
avalon_bridge.s12_debugaccess
in s12_debugaccessstd_logic
Definition: avalon_bridge.vhd:288
avalon_bridge.reset
in resetstd_logic
Definition: avalon_bridge.vhd:30
avalon_bridge.s19_burstcount
in s19_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:436
avalon_bridge.m19_readdatavalid
in m19_readdatavalidstd_logic
Definition: avalon_bridge.vhd:445
avalon_bridge.s22_address
in s22_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:504
avalon_bridge.BYTEEN_WIDTH
BYTEEN_WIDTHinteger := 4
Definition: avalon_bridge.vhd:24
avalon_bridge.s4_byteenable
in s4_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:111
avalon_bridge.s6_burstcount
in s6_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:150
avalon_bridge.m2_debugaccess
out m2_debugaccessstd_logic
Definition: avalon_bridge.vhd:78
avalon_bridge.s29_address
in s29_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:658
avalon_bridge.s27_writedata
in s27_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:613
avalon_bridge.m24_readdata
in m24_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:554
avalon_bridge.m18_burstcount
out m18_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:424
avalon_bridge.s15_byteenable
in s15_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:353
avalon_bridge.s6_writedata
in s6_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:151
avalon_bridge.m32_waitrequest
in m32_waitrequeststd_logic
Definition: avalon_bridge.vhd:729
avalon_bridge.m21_debugaccess
out m21_debugaccessstd_logic
Definition: avalon_bridge.vhd:496
avalon_bridge.m27_writedata
out m27_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:623
avalon_bridge.m7_writedata
out m7_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:183
avalon_bridge.m31_write
out m31_writestd_logic
Definition: avalon_bridge.vhd:713
avalon_bridge.s8_readdatavalid
out s8_readdatavalidstd_logic
Definition: avalon_bridge.vhd:193
avalon_bridge.s3_address
in s3_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:86
avalon_bridge.m7_read
out m7_readstd_logic
Definition: avalon_bridge.vhd:186
avalon_bridge.s8_byteenable
in s8_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:199
avalon_bridge.s16_burstcount
in s16_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:370
avalon_bridge.m2_readdatavalid
in m2_readdatavalidstd_logic
Definition: avalon_bridge.vhd:71
avalon_bridge.m17_waitrequest
in m17_waitrequeststd_logic
Definition: avalon_bridge.vhd:399
avalon_bridge.m14_debugaccess
out m14_debugaccessstd_logic
Definition: avalon_bridge.vhd:342
avalon_bridge.s13_waitrequest
out s13_waitrequeststd_logic
Definition: avalon_bridge.vhd:301
avalon_bridge.s27_burstcount
in s27_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:612
avalon_bridge.s7_burstcount
in s7_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:172
avalon_bridge.s30_readdatavalid
out s30_readdatavalidstd_logic
Definition: avalon_bridge.vhd:677
avalon_bridge.s9_write
in s9_writestd_logic
Definition: avalon_bridge.vhd:219
avalon_bridge.s21_waitrequest
out s21_waitrequeststd_logic
Definition: avalon_bridge.vhd:477
avalon_bridge.m22_byteenable
out m22_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:517
avalon_bridge.s12_readdatavalid
out s12_readdatavalidstd_logic
Definition: avalon_bridge.vhd:281
avalon_bridge.m5_write
out m5_writestd_logic
Definition: avalon_bridge.vhd:141
avalon_bridge.m23_waitrequest
in m23_waitrequeststd_logic
Definition: avalon_bridge.vhd:531
avalon_bridge.m22_burstcount
out m22_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:512
avalon_bridge.m4_writedata
out m4_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:117
avalon_bridge.s20_burstcount
in s20_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:458
avalon_bridge.s26_byteenable
in s26_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:595
avalon_bridge.m18_write
out m18_writestd_logic
Definition: avalon_bridge.vhd:427
avalon_bridge.s17_writedata
in s17_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:393
avalon_bridge.s24_debugaccess
in s24_debugaccessstd_logic
Definition: avalon_bridge.vhd:552
avalon_bridge.m28_debugaccess
out m28_debugaccessstd_logic
Definition: avalon_bridge.vhd:650
avalon_bridge.m31_readdatavalid
in m31_readdatavalidstd_logic
Definition: avalon_bridge.vhd:709
avalon_bridge.s9_read
in s9_readstd_logic
Definition: avalon_bridge.vhd:220
avalon_bridge.m19_read
out m19_readstd_logic
Definition: avalon_bridge.vhd:450
avalon_bridge.s29_write
in s29_writestd_logic
Definition: avalon_bridge.vhd:659
avalon_bridge.s26_burstcount
in s26_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:590
avalon_bridge.m9_writedata
out m9_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:227
avalon_bridge.s31_waitrequest
out s31_waitrequeststd_logic
Definition: avalon_bridge.vhd:697
avalon_bridge.s16_read
in s16_readstd_logic
Definition: avalon_bridge.vhd:374
avalon_bridge.m32_address
out m32_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:734
avalon_bridge.m14_address
out m14_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:338
avalon_bridge.m31_waitrequest
in m31_waitrequeststd_logic
Definition: avalon_bridge.vhd:707
avalon_bridge.s25_burstcount
in s25_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:568
avalon_bridge.s23_byteenable
in s23_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:529
avalon_bridge.m17_read
out m17_readstd_logic
Definition: avalon_bridge.vhd:406
avalon_bridge.s3_debugaccess
in s3_debugaccessstd_logic
Definition: avalon_bridge.vhd:90
avalon_bridge.s26_write
in s26_writestd_logic
Definition: avalon_bridge.vhd:593
avalon_bridge.m12_readdata
in m12_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:290
avalon_bridge.s31_debugaccess
in s31_debugaccessstd_logic
Definition: avalon_bridge.vhd:706
avalon_bridge.m23_debugaccess
out m23_debugaccessstd_logic
Definition: avalon_bridge.vhd:540
avalon_bridge.m1_burstcount
out m1_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:50
avalon_bridge.s11_readdata
out s11_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:258
avalon_bridge.m13_waitrequest
in m13_waitrequeststd_logic
Definition: avalon_bridge.vhd:311
avalon_bridge.m11_debugaccess
out m11_debugaccessstd_logic
Definition: avalon_bridge.vhd:276
avalon_bridge.m15_byteenable
out m15_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:363
avalon_bridge.s4_writedata
in s4_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:107
avalon_bridge.m22_writedata
out m22_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:513
avalon_bridge.s13_readdatavalid
out s13_readdatavalidstd_logic
Definition: avalon_bridge.vhd:303
avalon_bridge.m24_waitrequest
in m24_waitrequeststd_logic
Definition: avalon_bridge.vhd:553
avalon_bridge.m9_write
out m9_writestd_logic
Definition: avalon_bridge.vhd:229
avalon_bridge.m4_read
out m4_readstd_logic
Definition: avalon_bridge.vhd:120
avalon_bridge.m23_read
out m23_readstd_logic
Definition: avalon_bridge.vhd:538
avalon_bridge.m8_burstcount
out m8_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:204
avalon_bridge.s3_write
in s3_writestd_logic
Definition: avalon_bridge.vhd:87
avalon_bridge.m19_debugaccess
out m19_debugaccessstd_logic
Definition: avalon_bridge.vhd:452
avalon_bridge.s1_byteenable
in s1_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:45
avalon_bridge.m29_writedata
out m29_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:667
avalon_bridge.m24_read
out m24_readstd_logic
Definition: avalon_bridge.vhd:560
avalon_bridge.s26_writedata
in s26_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:591
avalon_bridge.s26_address
in s26_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:592
avalon_bridge.s22_writedata
in s22_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:503
avalon_bridge.m5_byteenable
out m5_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:143
avalon_bridge.m25_writedata
out m25_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:579
avalon_bridge.s23_waitrequest
out s23_waitrequeststd_logic
Definition: avalon_bridge.vhd:521
avalon_bridge.s22_readdatavalid
out s22_readdatavalidstd_logic
Definition: avalon_bridge.vhd:501
avalon_bridge.s30_byteenable
in s30_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:683
avalon_bridge.m31_read
out m31_readstd_logic
Definition: avalon_bridge.vhd:714
avalon_bridge.m32_readdatavalid
in m32_readdatavalidstd_logic
Definition: avalon_bridge.vhd:731
avalon_bridge.s5_address
in s5_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:130
avalon_bridge.m9_readdata
in m9_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:224
avalon_bridge.s32_byteenable
in s32_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:727
avalon_bridge.m1_writedata
out m1_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:51
avalon_bridge.s9_writedata
in s9_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:217
avalon_bridge.s21_byteenable
in s21_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:485
avalon_bridge.s5_byteenable
in s5_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:133
avalon_bridge.s4_read
in s4_readstd_logic
Definition: avalon_bridge.vhd:110
avalon_bridge.m23_writedata
out m23_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:535
avalon_bridge.m7_byteenable
out m7_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:187
avalon_bridge.m8_readdata
in m8_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:202
avalon_bridge.s15_debugaccess
in s15_debugaccessstd_logic
Definition: avalon_bridge.vhd:354
avalon_bridge.m17_writedata
out m17_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:403
avalon_bridge.m14_waitrequest
in m14_waitrequeststd_logic
Definition: avalon_bridge.vhd:333
avalon_bridge.s17_write
in s17_writestd_logic
Definition: avalon_bridge.vhd:395
avalon_bridge.s3_waitrequest
out s3_waitrequeststd_logic
Definition: avalon_bridge.vhd:81
avalon_bridge.m11_waitrequest
in m11_waitrequeststd_logic
Definition: avalon_bridge.vhd:267
avalon_bridge.s4_readdatavalid
out s4_readdatavalidstd_logic
Definition: avalon_bridge.vhd:105
avalon_bridge.m15_address
out m15_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:360
avalon_bridge.s29_readdatavalid
out s29_readdatavalidstd_logic
Definition: avalon_bridge.vhd:655
avalon_bridge.m30_read
out m30_readstd_logic
Definition: avalon_bridge.vhd:692
avalon_bridge.s16_address
in s16_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:372
avalon_bridge.m9_readdatavalid
in m9_readdatavalidstd_logic
Definition: avalon_bridge.vhd:225
avalon_bridge.m9_read
out m9_readstd_logic
Definition: avalon_bridge.vhd:230
avalon_bridge.s1_waitrequest
out s1_waitrequeststd_logic
Definition: avalon_bridge.vhd:37
avalon_bridge.m27_readdatavalid
in m27_readdatavalidstd_logic
Definition: avalon_bridge.vhd:621
avalon_bridge.m13_readdatavalid
in m13_readdatavalidstd_logic
Definition: avalon_bridge.vhd:313
avalon_bridge.clk
in clkstd_logic
Definition: avalon_bridge.vhd:29
avalon_bridge.m6_readdatavalid
in m6_readdatavalidstd_logic
Definition: avalon_bridge.vhd:159
avalon_bridge.s8_writedata
in s8_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:195
avalon_bridge.m26_debugaccess
out m26_debugaccessstd_logic
Definition: avalon_bridge.vhd:606
avalon_bridge.m30_readdatavalid
in m30_readdatavalidstd_logic
Definition: avalon_bridge.vhd:687
avalon_bridge.m16_read
out m16_readstd_logic
Definition: avalon_bridge.vhd:384
avalon_bridge.s2_byteenable
in s2_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:67
avalon_bridge.s3_byteenable
in s3_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:89
avalon_bridge.s15_burstcount
in s15_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:348
avalon_bridge.m1_byteenable
out m1_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:55
avalon_bridge.s27_readdatavalid
out s27_readdatavalidstd_logic
Definition: avalon_bridge.vhd:611
avalon_bridge.s25_read
in s25_readstd_logic
Definition: avalon_bridge.vhd:572
avalon_bridge.m23_write
out m23_writestd_logic
Definition: avalon_bridge.vhd:537
avalon_bridge.s13_debugaccess
in s13_debugaccessstd_logic
Definition: avalon_bridge.vhd:310
avalon_bridge.s4_burstcount
in s4_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:106
avalon_bridge.m2_burstcount
out m2_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:72
avalon_bridge.s7_readdatavalid
out s7_readdatavalidstd_logic
Definition: avalon_bridge.vhd:171
avalon_bridge.s20_read
in s20_readstd_logic
Definition: avalon_bridge.vhd:462
avalon_bridge.m12_byteenable
out m12_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:297
avalon_bridge.m8_write
out m8_writestd_logic
Definition: avalon_bridge.vhd:207
avalon_bridge.s6_write
in s6_writestd_logic
Definition: avalon_bridge.vhd:153
avalon_bridge.m26_readdata
in m26_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:598
avalon_bridge.s7_write
in s7_writestd_logic
Definition: avalon_bridge.vhd:175
avalon_bridge.m2_writedata
out m2_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:73
avalon_bridge.s31_byteenable
in s31_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:705
avalon_bridge.m1_readdata
in m1_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:48
avalon_bridge.s20_debugaccess
in s20_debugaccessstd_logic
Definition: avalon_bridge.vhd:464
avalon_bridge.s25_readdata
out s25_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:566
avalon_bridge.m12_read
out m12_readstd_logic
Definition: avalon_bridge.vhd:296
avalon_bridge.s2_read
in s2_readstd_logic
Definition: avalon_bridge.vhd:66
avalon_bridge.s30_readdata
out s30_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:676
avalon_bridge.s27_byteenable
in s27_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:617
avalon_bridge.s31_write
in s31_writestd_logic
Definition: avalon_bridge.vhd:703
avalon_bridge.m30_burstcount
out m30_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:688
avalon_bridge.s7_read
in s7_readstd_logic
Definition: avalon_bridge.vhd:176
avalon_bridge.m14_readdatavalid
in m14_readdatavalidstd_logic
Definition: avalon_bridge.vhd:335
avalon_bridge.s5_debugaccess
in s5_debugaccessstd_logic
Definition: avalon_bridge.vhd:134
avalon_bridge.s1_writedata
in s1_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:41
avalon_bridge.m19_burstcount
out m19_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:446
avalon_bridge.ADDRESS_WIDTH
ADDRESS_WIDTHinteger := 32
Definition: avalon_bridge.vhd:22
avalon_bridge.s30_read
in s30_readstd_logic
Definition: avalon_bridge.vhd:682
avalon_bridge.s15_readdatavalid
out s15_readdatavalidstd_logic
Definition: avalon_bridge.vhd:347
avalon_bridge.s20_waitrequest
out s20_waitrequeststd_logic
Definition: avalon_bridge.vhd:455
avalon_bridge.m20_write
out m20_writestd_logic
Definition: avalon_bridge.vhd:471
avalon_bridge.s21_write
in s21_writestd_logic
Definition: avalon_bridge.vhd:483
avalon_bridge.m32_byteenable
out m32_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:737
avalon_bridge.m20_waitrequest
in m20_waitrequeststd_logic
Definition: avalon_bridge.vhd:465
avalon_bridge.s10_byteenable
in s10_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:243
avalon_bridge.m25_read
out m25_readstd_logic
Definition: avalon_bridge.vhd:582
avalon_bridge.m10_readdata
in m10_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:246
avalon_bridge.s32_write
in s32_writestd_logic
Definition: avalon_bridge.vhd:725
avalon_bridge.m25_debugaccess
out m25_debugaccessstd_logic
Definition: avalon_bridge.vhd:584
avalon_bridge.s16_debugaccess
in s16_debugaccessstd_logic
Definition: avalon_bridge.vhd:376
avalon_bridge.m24_byteenable
out m24_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:561
avalon_bridge.m18_readdata
in m18_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:422
avalon_bridge.m5_burstcount
out m5_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:138
avalon_bridge.s19_waitrequest
out s19_waitrequeststd_logic
Definition: avalon_bridge.vhd:433
avalon_bridge.m6_readdata
in m6_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:158
avalon_bridge.m31_byteenable
out m31_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:715
avalon_bridge.s28_waitrequest
out s28_waitrequeststd_logic
Definition: avalon_bridge.vhd:631
avalon_bridge.m29_readdatavalid
in m29_readdatavalidstd_logic
Definition: avalon_bridge.vhd:665
avalon_bridge.s4_write
in s4_writestd_logic
Definition: avalon_bridge.vhd:109
avalon_bridge.s6_readdatavalid
out s6_readdatavalidstd_logic
Definition: avalon_bridge.vhd:149
avalon_bridge.s17_waitrequest
out s17_waitrequeststd_logic
Definition: avalon_bridge.vhd:389
avalon_bridge.m10_burstcount
out m10_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:248
avalon_bridge.s3_read
in s3_readstd_logic
Definition: avalon_bridge.vhd:88
avalon_bridge.m30_write
out m30_writestd_logic
Definition: avalon_bridge.vhd:691
avalon_bridge.s6_address
in s6_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:152
avalon_bridge.m15_debugaccess
out m15_debugaccessstd_logic
Definition: avalon_bridge.vhd:364
avalon_bridge.m30_byteenable
out m30_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:693
avalon_bridge.s21_address
in s21_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:482
avalon_bridge.m26_writedata
out m26_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:601
avalon_bridge.s25_readdatavalid
out s25_readdatavalidstd_logic
Definition: avalon_bridge.vhd:567
avalon_bridge.s31_burstcount
in s31_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:700
avalon_bridge.s22_burstcount
in s22_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:502
avalon_bridge.m27_readdata
in m27_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:620
avalon_bridge.m26_waitrequest
in m26_waitrequeststd_logic
Definition: avalon_bridge.vhd:597
avalon_bridge.m22_write
out m22_writestd_logic
Definition: avalon_bridge.vhd:515
avalon_bridge.s2_debugaccess
in s2_debugaccessstd_logic
Definition: avalon_bridge.vhd:68
avalon_bridge.s22_waitrequest
out s22_waitrequeststd_logic
Definition: avalon_bridge.vhd:499
avalon_bridge.m18_address
out m18_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:426
avalon_bridge.s26_debugaccess
in s26_debugaccessstd_logic
Definition: avalon_bridge.vhd:596
avalon_bridge.m3_read
out m3_readstd_logic
Definition: avalon_bridge.vhd:98
avalon_bridge.s13_readdata
out s13_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:302
avalon_bridge.m21_address
out m21_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:492
avalon_bridge.m30_waitrequest
in m30_waitrequeststd_logic
Definition: avalon_bridge.vhd:685
avalon_bridge.s8_burstcount
in s8_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:194
avalon_bridge.s8_debugaccess
in s8_debugaccessstd_logic
Definition: avalon_bridge.vhd:200
avalon_bridge.m12_readdatavalid
in m12_readdatavalidstd_logic
Definition: avalon_bridge.vhd:291
avalon_bridge.m8_readdatavalid
in m8_readdatavalidstd_logic
Definition: avalon_bridge.vhd:203
avalon_bridge.m10_address
out m10_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:250
avalon_bridge.s21_debugaccess
in s21_debugaccessstd_logic
Definition: avalon_bridge.vhd:486
avalon_bridge.s13_read
in s13_readstd_logic
Definition: avalon_bridge.vhd:308
avalon_bridge.m2_waitrequest
in m2_waitrequeststd_logic
Definition: avalon_bridge.vhd:69
avalon_bridge.m28_waitrequest
in m28_waitrequeststd_logic
Definition: avalon_bridge.vhd:641
avalon_bridge.s23_debugaccess
in s23_debugaccessstd_logic
Definition: avalon_bridge.vhd:530
avalon_bridge.m21_byteenable
out m21_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:495
avalon_bridge.m3_readdatavalid
in m3_readdatavalidstd_logic
Definition: avalon_bridge.vhd:93
avalon_bridge.m20_writedata
out m20_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:469
avalon_bridge.m3_write
out m3_writestd_logic
Definition: avalon_bridge.vhd:97
avalon_bridge.m3_debugaccess
out m3_debugaccessstd_logic
Definition: avalon_bridge.vhd:100
avalon_bridge.s19_write
in s19_writestd_logic
Definition: avalon_bridge.vhd:439
avalon_bridge.s2_waitrequest
out s2_waitrequeststd_logic
Definition: avalon_bridge.vhd:59
avalon_bridge.s11_address
in s11_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:262
avalon_bridge.m4_readdatavalid
in m4_readdatavalidstd_logic
Definition: avalon_bridge.vhd:115
avalon_bridge.m28_writedata
out m28_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:645
avalon_bridge.s5_write
in s5_writestd_logic
Definition: avalon_bridge.vhd:131
avalon_bridge.m19_writedata
out m19_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:447
avalon_bridge.m13_write
out m13_writestd_logic
Definition: avalon_bridge.vhd:317
avalon_bridge.s30_burstcount
in s30_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:678
avalon_bridge.m27_byteenable
out m27_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:627
avalon_bridge.m17_debugaccess
out m17_debugaccessstd_logic
Definition: avalon_bridge.vhd:408
avalon_bridge.s21_readdatavalid
out s21_readdatavalidstd_logic
Definition: avalon_bridge.vhd:479
avalon_bridge.s19_readdatavalid
out s19_readdatavalidstd_logic
Definition: avalon_bridge.vhd:435
avalon_bridge.m20_address
out m20_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:470
avalon_bridge.s14_writedata
in s14_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:327
avalon_bridge.s18_readdatavalid
out s18_readdatavalidstd_logic
Definition: avalon_bridge.vhd:413
avalon_bridge.m32_debugaccess
out m32_debugaccessstd_logic
Definition: avalon_bridge.vhd:740
avalon_bridge.m25_waitrequest
in m25_waitrequeststd_logic
Definition: avalon_bridge.vhd:575
avalon_bridge.s23_readdata
out s23_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:522
avalon_bridge.s16_byteenable
in s16_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:375
avalon_bridge.s29_byteenable
in s29_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:661
avalon_bridge.m18_writedata
out m18_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:425
avalon_bridge.m3_byteenable
out m3_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:99
avalon_bridge.m28_address
out m28_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:646
avalon_bridge.m4_byteenable
out m4_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:121
avalon_bridge.s20_address
in s20_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:460
avalon_bridge.s22_debugaccess
in s22_debugaccessstd_logic
Definition: avalon_bridge.vhd:508
avalon_bridge.m5_writedata
out m5_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:139
avalon_bridge.s25_waitrequest
out s25_waitrequeststd_logic
Definition: avalon_bridge.vhd:565
avalon_bridge.s15_writedata
in s15_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:349
avalon_bridge.s15_waitrequest
out s15_waitrequeststd_logic
Definition: avalon_bridge.vhd:345
avalon_bridge.s13_burstcount
in s13_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:304
avalon_bridge.s9_burstcount
in s9_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:216
avalon_bridge.m26_address
out m26_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:602
avalon_bridge.s11_writedata
in s11_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:261
avalon_bridge.s6_readdata
out s6_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:148
avalon_bridge.s24_byteenable
in s24_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:551
avalon_bridge.m4_waitrequest
in m4_waitrequeststd_logic
Definition: avalon_bridge.vhd:113
avalon_bridge.m28_readdatavalid
in m28_readdatavalidstd_logic
Definition: avalon_bridge.vhd:643
avalon_bridge.s11_write
in s11_writestd_logic
Definition: avalon_bridge.vhd:263
avalon_bridge.m17_readdata
in m17_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:400
avalon_bridge.s30_debugaccess
in s30_debugaccessstd_logic
Definition: avalon_bridge.vhd:684
avalon_bridge.m11_byteenable
out m11_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:275
avalon_bridge.s13_byteenable
in s13_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:309
avalon_bridge.m27_read
out m27_readstd_logic
Definition: avalon_bridge.vhd:626
avalon_bridge.s22_readdata
out s22_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:500
avalon_bridge.s32_readdatavalid
out s32_readdatavalidstd_logic
Definition: avalon_bridge.vhd:721
avalon_bridge.m25_readdata
in m25_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:576
avalon_bridge.s10_waitrequest
out s10_waitrequeststd_logic
Definition: avalon_bridge.vhd:235
avalon_bridge.s9_waitrequest
out s9_waitrequeststd_logic
Definition: avalon_bridge.vhd:213
avalon_bridge.s19_read
in s19_readstd_logic
Definition: avalon_bridge.vhd:440
avalon_bridge.m20_readdatavalid
in m20_readdatavalidstd_logic
Definition: avalon_bridge.vhd:467
avalon_bridge.m12_waitrequest
in m12_waitrequeststd_logic
Definition: avalon_bridge.vhd:289
avalon_bridge.s10_burstcount
in s10_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:238
avalon_bridge.m28_byteenable
out m28_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:649
avalon_bridge.m21_readdatavalid
in m21_readdatavalidstd_logic
Definition: avalon_bridge.vhd:489
avalon_bridge.s32_readdata
out s32_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:720
avalon_bridge.s24_writedata
in s24_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:547
avalon_bridge.m20_read
out m20_readstd_logic
Definition: avalon_bridge.vhd:472
avalon_bridge.m5_read
out m5_readstd_logic
Definition: avalon_bridge.vhd:142
avalon_bridge.m19_address
out m19_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:448
avalon_bridge.s23_write
in s23_writestd_logic
Definition: avalon_bridge.vhd:527
avalon_bridge.m4_address
out m4_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:118
avalon_bridge.s20_readdatavalid
out s20_readdatavalidstd_logic
Definition: avalon_bridge.vhd:457
avalon_bridge.m13_readdata
in m13_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:312
avalon_bridge.m17_readdatavalid
in m17_readdatavalidstd_logic
Definition: avalon_bridge.vhd:401
avalon_bridge.s15_readdata
out s15_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:346
avalon_bridge.m18_readdatavalid
in m18_readdatavalidstd_logic
Definition: avalon_bridge.vhd:423
avalon_bridge.s26_read
in s26_readstd_logic
Definition: avalon_bridge.vhd:594
avalon_bridge.m21_waitrequest
in m21_waitrequeststd_logic
Definition: avalon_bridge.vhd:487
avalon_bridge.m2_address
out m2_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:74
avalon_bridge.s7_waitrequest
out s7_waitrequeststd_logic
Definition: avalon_bridge.vhd:169
avalon_bridge.m29_debugaccess
out m29_debugaccessstd_logic
Definition: avalon_bridge.vhd:672
avalon_bridge.s5_readdata
out s5_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:126
avalon_bridge.s1_read
in s1_readstd_logic
Definition: avalon_bridge.vhd:44
avalon_bridge.s9_readdatavalid
out s9_readdatavalidstd_logic
Definition: avalon_bridge.vhd:215
avalon_bridge.m18_waitrequest
in m18_waitrequeststd_logic
Definition: avalon_bridge.vhd:421
avalon_bridge.s2_write
in s2_writestd_logic
Definition: avalon_bridge.vhd:65
avalon_bridge.m13_debugaccess
out m13_debugaccessstd_logic
Definition: avalon_bridge.vhd:320
avalon_bridge.s30_writedata
in s30_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:679
avalon_bridge.s4_waitrequest
out s4_waitrequeststd_logic
Definition: avalon_bridge.vhd:103
avalon_bridge.m32_readdata
in m32_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:730
avalon_bridge.m3_writedata
out m3_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:95
avalon_bridge.m16_byteenable
out m16_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:385
avalon_bridge.s24_waitrequest
out s24_waitrequeststd_logic
Definition: avalon_bridge.vhd:543
avalon_bridge.s21_writedata
in s21_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:481
avalon_bridge.s2_burstcount
in s2_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:62
avalon_bridge.s28_write
in s28_writestd_logic
Definition: avalon_bridge.vhd:637
avalon_bridge.s19_address
in s19_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:438
avalon_bridge.s1_write
in s1_writestd_logic
Definition: avalon_bridge.vhd:43
avalon_bridge.s13_write
in s13_writestd_logic
Definition: avalon_bridge.vhd:307
avalon_bridge.s8_waitrequest
out s8_waitrequeststd_logic
Definition: avalon_bridge.vhd:191
avalon_bridge
Definition: avalon_bridge.vhd:16
avalon_bridge.m25_byteenable
out m25_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:583
avalon_bridge.m12_writedata
out m12_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:293
avalon_bridge.s23_read
in s23_readstd_logic
Definition: avalon_bridge.vhd:528
avalon_bridge.s10_debugaccess
in s10_debugaccessstd_logic
Definition: avalon_bridge.vhd:244
avalon_bridge.m20_burstcount
out m20_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:468
avalon_bridge.m8_waitrequest
in m8_waitrequeststd_logic
Definition: avalon_bridge.vhd:201
avalon_bridge.s28_address
in s28_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:636
avalon_bridge.s19_debugaccess
in s19_debugaccessstd_logic
Definition: avalon_bridge.vhd:442
avalon_bridge.s29_readdata
out s29_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:654
avalon_bridge.s18_byteenable
in s18_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:419
avalon_bridge.s24_burstcount
in s24_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:546
avalon_bridge.m23_readdatavalid
in m23_readdatavalidstd_logic
Definition: avalon_bridge.vhd:533
avalon_bridge.m10_readdatavalid
in m10_readdatavalidstd_logic
Definition: avalon_bridge.vhd:247
avalon_bridge.m24_debugaccess
out m24_debugaccessstd_logic
Definition: avalon_bridge.vhd:562
avalon_bridge.s4_debugaccess
in s4_debugaccessstd_logic
Definition: avalon_bridge.vhd:112
avalon_bridge.s14_readdatavalid
out s14_readdatavalidstd_logic
Definition: avalon_bridge.vhd:325
avalon_bridge.s11_debugaccess
in s11_debugaccessstd_logic
Definition: avalon_bridge.vhd:266
avalon_bridge.s17_burstcount
in s17_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:392
avalon_bridge.s3_burstcount
in s3_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:84
avalon_bridge.m16_writedata
out m16_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:381
avalon_bridge.s1_burstcount
in s1_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:40
avalon_bridge.m1_readdatavalid
in m1_readdatavalidstd_logic
Definition: avalon_bridge.vhd:49
avalon_bridge.m22_read
out m22_readstd_logic
Definition: avalon_bridge.vhd:516
avalon_bridge.m32_write
out m32_writestd_logic
Definition: avalon_bridge.vhd:735
avalon_bridge.m22_waitrequest
in m22_waitrequeststd_logic
Definition: avalon_bridge.vhd:509
avalon_bridge.m18_read
out m18_readstd_logic
Definition: avalon_bridge.vhd:428
avalon_bridge.s7_readdata
out s7_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:170
avalon_bridge.m8_read
out m8_readstd_logic
Definition: avalon_bridge.vhd:208
avalon_bridge.s32_burstcount
in s32_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:722
avalon_bridge.s9_address
in s9_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:218
avalon_bridge.m30_writedata
out m30_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:689
avalon_bridge.m5_readdata
in m5_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:136
avalon_bridge.m24_address
out m24_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:558
avalon_bridge.s18_read
in s18_readstd_logic
Definition: avalon_bridge.vhd:418
avalon_bridge.m6_waitrequest
in m6_waitrequeststd_logic
Definition: avalon_bridge.vhd:157
avalon_bridge.m18_debugaccess
out m18_debugaccessstd_logic
Definition: avalon_bridge.vhd:430
avalon_bridge.m4_debugaccess
out m4_debugaccessstd_logic
Definition: avalon_bridge.vhd:122
avalon_bridge.s12_readdata
out s12_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:280
avalon_bridge.m6_burstcount
out m6_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:160
avalon_bridge.s2_readdata
out s2_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:60
avalon_bridge.s29_read
in s29_readstd_logic
Definition: avalon_bridge.vhd:660
avalon_bridge.m6_debugaccess
out m6_debugaccessstd_logic
Definition: avalon_bridge.vhd:166
avalon_bridge.s10_writedata
in s10_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:239
avalon_bridge.s18_waitrequest
out s18_waitrequeststd_logic
Definition: avalon_bridge.vhd:411
avalon_bridge.m29_read
out m29_readstd_logic
Definition: avalon_bridge.vhd:670
avalon_bridge.s29_debugaccess
in s29_debugaccessstd_logic
Definition: avalon_bridge.vhd:662
avalon_bridge.m11_address
out m11_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:272
avalon_bridge.m4_write
out m4_writestd_logic
Definition: avalon_bridge.vhd:119
avalon_bridge.m29_readdata
in m29_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:664
avalon_bridge.s32_writedata
in s32_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:723
avalon_bridge.s18_readdata
out s18_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:412
avalon_bridge.m8_debugaccess
out m8_debugaccessstd_logic
Definition: avalon_bridge.vhd:210
avalon_bridge.m21_write
out m21_writestd_logic
Definition: avalon_bridge.vhd:493
avalon_bridge.s29_burstcount
in s29_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:656
avalon_bridge.AM1
Definition: avalon_bridge.vhd:744
avalon_bridge.m32_writedata
out m32_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:733
avalon_bridge.s27_waitrequest
out s27_waitrequeststd_logic
Definition: avalon_bridge.vhd:609
avalon_bridge.s23_writedata
in s23_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:525
avalon_bridge.m6_write
out m6_writestd_logic
Definition: avalon_bridge.vhd:163
avalon_bridge.s5_burstcount
in s5_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:128
avalon_bridge.m11_readdata
in m11_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:268
avalon_bridge.s16_readdatavalid
out s16_readdatavalidstd_logic
Definition: avalon_bridge.vhd:369
avalon_bridge.m7_write
out m7_writestd_logic
Definition: avalon_bridge.vhd:185
avalon_bridge.m2_read
out m2_readstd_logic
Definition: avalon_bridge.vhd:76
avalon_bridge.m15_readdata
in m15_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:356
avalon_bridge.m29_address
out m29_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:668
avalon_bridge.m28_burstcount
out m28_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:644
avalon_bridge.m12_address
out m12_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:294
avalon_bridge.m14_read
out m14_readstd_logic
Definition: avalon_bridge.vhd:340
avalon_bridge.m27_waitrequest
in m27_waitrequeststd_logic
Definition: avalon_bridge.vhd:619
avalon_bridge.m16_write
out m16_writestd_logic
Definition: avalon_bridge.vhd:383
avalon_bridge.s25_debugaccess
in s25_debugaccessstd_logic
Definition: avalon_bridge.vhd:574
avalon_bridge.s13_writedata
in s13_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:305
avalon_bridge.m25_readdatavalid
in m25_readdatavalidstd_logic
Definition: avalon_bridge.vhd:577
avalon_bridge.m28_read
out m28_readstd_logic
Definition: avalon_bridge.vhd:648
avalon_bridge.s17_read
in s17_readstd_logic
Definition: avalon_bridge.vhd:396
avalon_bridge.m22_debugaccess
out m22_debugaccessstd_logic
Definition: avalon_bridge.vhd:518
avalon_bridge.s16_readdata
out s16_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:368
avalon_bridge.m9_address
out m9_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:228
avalon_bridge.s28_read
in s28_readstd_logic
Definition: avalon_bridge.vhd:638
avalon_bridge.m31_writedata
out m31_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:711
avalon_bridge.m7_waitrequest
in m7_waitrequeststd_logic
Definition: avalon_bridge.vhd:179
avalon_bridge.s18_burstcount
in s18_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:414
avalon_bridge.s1_address
in s1_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:42
avalon_bridge.s19_byteenable
in s19_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:441
avalon_bridge.s7_address
in s7_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:174
avalon_bridge.s26_readdatavalid
out s26_readdatavalidstd_logic
Definition: avalon_bridge.vhd:589
avalon_bridge.m7_readdatavalid
in m7_readdatavalidstd_logic
Definition: avalon_bridge.vhd:181
avalon_bridge.m13_read
out m13_readstd_logic
Definition: avalon_bridge.vhd:318
avalon_bridge.m15_read
out m15_readstd_logic
Definition: avalon_bridge.vhd:362
avalon_bridge.m13_burstcount
out m13_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:314
avalon_bridge.s9_debugaccess
in s9_debugaccessstd_logic
Definition: avalon_bridge.vhd:222
avalon_bridge.s8_readdata
out s8_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:192
avalon_bridge.s31_readdata
out s31_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:698
avalon_bridge.s32_debugaccess
in s32_debugaccessstd_logic
Definition: avalon_bridge.vhd:728
avalon_bridge.s10_write
in s10_writestd_logic
Definition: avalon_bridge.vhd:241
avalon_bridge.m16_debugaccess
out m16_debugaccessstd_logic
Definition: avalon_bridge.vhd:386
avalon_bridge.m30_readdata
in m30_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:686
avalon_bridge.m8_byteenable
out m8_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:209
avalon_bridge.m11_readdatavalid
in m11_readdatavalidstd_logic
Definition: avalon_bridge.vhd:269
avalon_bridge.s11_waitrequest
out s11_waitrequeststd_logic
Definition: avalon_bridge.vhd:257
avalon_bridge.s5_waitrequest
out s5_waitrequeststd_logic
Definition: avalon_bridge.vhd:125
avalon_bridge.s7_writedata
in s7_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:173
avalon_bridge.m1_waitrequest
in m1_waitrequeststd_logic
Definition: avalon_bridge.vhd:47
avalon_bridge.s30_address
in s30_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:680
avalon_bridge.m27_address
out m27_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:624
avalon_bridge.m11_read
out m11_readstd_logic
Definition: avalon_bridge.vhd:274
avalon_bridge.m23_burstcount
out m23_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:534
avalon_bridge.s6_byteenable
in s6_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:155
avalon_bridge.m10_read
out m10_readstd_logic
Definition: avalon_bridge.vhd:252
avalon_bridge.m31_burstcount
out m31_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:710
avalon_bridge.m31_debugaccess
out m31_debugaccessstd_logic
Definition: avalon_bridge.vhd:716
avalon_bridge.m26_byteenable
out m26_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:605
avalon_bridge.s17_debugaccess
in s17_debugaccessstd_logic
Definition: avalon_bridge.vhd:398
avalon_bridge.m6_read
out m6_readstd_logic
Definition: avalon_bridge.vhd:164
avalon_bridge.m15_burstcount
out m15_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:358
avalon_bridge.m16_waitrequest
in m16_waitrequeststd_logic
Definition: avalon_bridge.vhd:377
avalon_bridge.s12_address
in s12_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:284
avalon_bridge.m24_writedata
out m24_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:557
avalon_bridge.m13_byteenable
out m13_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:319
avalon_bridge.m14_readdata
in m14_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:334
avalon_bridge.s24_readdatavalid
out s24_readdatavalidstd_logic
Definition: avalon_bridge.vhd:545
avalon_bridge.m1_debugaccess
out m1_debugaccessstd_logic
Definition: avalon_bridge.vhd:56
avalon_bridge.s14_waitrequest
out s14_waitrequeststd_logic
Definition: avalon_bridge.vhd:323
avalon_bridge.m15_writedata
out m15_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:359
avalon_bridge.m24_burstcount
out m24_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:556
avalon_bridge.s8_write
in s8_writestd_logic
Definition: avalon_bridge.vhd:197
avalon_bridge.m10_write
out m10_writestd_logic
Definition: avalon_bridge.vhd:251
avalon_bridge.s14_byteenable
in s14_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:331
avalon_bridge.s10_readdata
out s10_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:236
avalon_bridge.m27_debugaccess
out m27_debugaccessstd_logic
Definition: avalon_bridge.vhd:628
avalon_bridge.m3_burstcount
out m3_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:94
avalon_bridge.m16_readdata
in m16_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:378
avalon_bridge.m11_write
out m11_writestd_logic
Definition: avalon_bridge.vhd:273
avalon_bridge.m7_debugaccess
out m7_debugaccessstd_logic
Definition: avalon_bridge.vhd:188
avalon_bridge.s11_read
in s11_readstd_logic
Definition: avalon_bridge.vhd:264
avalon_bridge.m6_byteenable
out m6_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:165
avalon_bridge.s18_debugaccess
in s18_debugaccessstd_logic
Definition: avalon_bridge.vhd:420
avalon_bridge.m16_readdatavalid
in m16_readdatavalidstd_logic
Definition: avalon_bridge.vhd:379
avalon_bridge.s30_write
in s30_writestd_logic
Definition: avalon_bridge.vhd:681
avalon_bridge.s20_byteenable
in s20_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:463
avalon_bridge.m10_byteenable
out m10_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:253
avalon_bridge.s1_readdata
out s1_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:38
avalon_bridge.m7_address
out m7_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:184
avalon_bridge.m4_burstcount
out m4_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:116
avalon_bridge.s31_writedata
in s31_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:701
avalon_bridge.s15_address
in s15_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:350
avalon_bridge.s20_write
in s20_writestd_logic
Definition: avalon_bridge.vhd:461
avalon_bridge.s14_burstcount
in s14_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:326
avalon_bridge.m20_debugaccess
out m20_debugaccessstd_logic
Definition: avalon_bridge.vhd:474
avalon_bridge.m10_debugaccess
out m10_debugaccessstd_logic
Definition: avalon_bridge.vhd:254
avalon_bridge.s27_address
in s27_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:614
avalon_bridge.m9_waitrequest
in m9_waitrequeststd_logic
Definition: avalon_bridge.vhd:223
avalon_bridge.s7_byteenable
in s7_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:177
avalon_bridge.s14_read
in s14_readstd_logic
Definition: avalon_bridge.vhd:330
avalon_bridge.m9_burstcount
out m9_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:226
avalon_bridge.m14_burstcount
out m14_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:336
avalon_bridge.s30_waitrequest
out s30_waitrequeststd_logic
Definition: avalon_bridge.vhd:675
avalon_bridge.s12_write
in s12_writestd_logic
Definition: avalon_bridge.vhd:285
avalon_bridge.m16_address
out m16_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:382
avalon_bridge.m1_write
out m1_writestd_logic
Definition: avalon_bridge.vhd:53
avalon_bridge.m24_readdatavalid
in m24_readdatavalidstd_logic
Definition: avalon_bridge.vhd:555
avalon_bridge.s10_read
in s10_readstd_logic
Definition: avalon_bridge.vhd:242
avalon_bridge.m2_write
out m2_writestd_logic
Definition: avalon_bridge.vhd:75
avalon_bridge.s28_debugaccess
in s28_debugaccessstd_logic
Definition: avalon_bridge.vhd:640
avalon_bridge.m16_burstcount
out m16_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:380
avalon_bridge.s24_address
in s24_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:548
avalon_bridge.s14_readdata
out s14_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:324
avalon_bridge.s9_readdata
out s9_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:214
avalon_bridge.m5_debugaccess
out m5_debugaccessstd_logic
Definition: avalon_bridge.vhd:144
avalon_bridge.s22_byteenable
in s22_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:507
avalon_bridge.s24_write
in s24_writestd_logic
Definition: avalon_bridge.vhd:549
avalon_bridge.m14_byteenable
out m14_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:341
avalon_bridge.m13_writedata
out m13_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:315
avalon_bridge.s24_read
in s24_readstd_logic
Definition: avalon_bridge.vhd:550
avalon_bridge.s8_read
in s8_readstd_logic
Definition: avalon_bridge.vhd:198
avalon_bridge.s17_byteenable
in s17_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:397
avalon_bridge.s17_readdata
out s17_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:390
avalon_bridge.m11_burstcount
out m11_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:270
avalon_bridge.m3_waitrequest
in m3_waitrequeststd_logic
Definition: avalon_bridge.vhd:91
avalon_bridge.m32_burstcount
out m32_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:732
avalon_bridge.s31_address
in s31_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:702
avalon_bridge.m10_writedata
out m10_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:249
avalon_bridge.m29_write
out m29_writestd_logic
Definition: avalon_bridge.vhd:669
avalon_bridge.m21_readdata
in m21_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:488
avalon_bridge.m31_readdata
in m31_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:708
avalon_bridge.m15_write
out m15_writestd_logic
Definition: avalon_bridge.vhd:361
avalon_bridge.s2_readdatavalid
out s2_readdatavalidstd_logic
Definition: avalon_bridge.vhd:61
avalon_bridge.s16_write
in s16_writestd_logic
Definition: avalon_bridge.vhd:373
avalon_bridge.s32_waitrequest
out s32_waitrequeststd_logic
Definition: avalon_bridge.vhd:719
avalon_bridge.s13_address
in s13_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:306
avalon_bridge.m17_byteenable
out m17_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:407
avalon_bridge.s2_writedata
in s2_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:63
avalon_bridge.m10_waitrequest
in m10_waitrequeststd_logic
Definition: avalon_bridge.vhd:245
avalon_bridge.m29_waitrequest
in m29_waitrequeststd_logic
Definition: avalon_bridge.vhd:663
avalon_bridge.s12_burstcount
in s12_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:282
avalon_bridge.s6_waitrequest
out s6_waitrequeststd_logic
Definition: avalon_bridge.vhd:147
avalon_bridge.m30_address
out m30_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:690
avalon_bridge.s27_readdata
out s27_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:610
avalon_bridge.s6_read
in s6_readstd_logic
Definition: avalon_bridge.vhd:154
avalon_bridge.m32_read
out m32_readstd_logic
Definition: avalon_bridge.vhd:736
avalon_bridge.m30_debugaccess
out m30_debugaccessstd_logic
Definition: avalon_bridge.vhd:694
avalon_bridge.s27_write
in s27_writestd_logic
Definition: avalon_bridge.vhd:615
avalon_bridge.m27_write
out m27_writestd_logic
Definition: avalon_bridge.vhd:625
avalon_bridge.s25_write
in s25_writestd_logic
Definition: avalon_bridge.vhd:571
avalon_bridge.s3_writedata
in s3_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:85
avalon_bridge.s11_burstcount
in s11_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:260
avalon_bridge.m5_readdatavalid
in m5_readdatavalidstd_logic
Definition: avalon_bridge.vhd:137
avalon_bridge.m22_readdatavalid
in m22_readdatavalidstd_logic
Definition: avalon_bridge.vhd:511
avalon_bridge.m24_write
out m24_writestd_logic
Definition: avalon_bridge.vhd:559
avalon_bridge.s28_writedata
in s28_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:635
avalon_bridge.m26_readdatavalid
in m26_readdatavalidstd_logic
Definition: avalon_bridge.vhd:599
avalon_bridge.m26_burstcount
out m26_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:600
avalon_bridge.m12_debugaccess
out m12_debugaccessstd_logic
Definition: avalon_bridge.vhd:298
avalon_bridge.s3_readdatavalid
out s3_readdatavalidstd_logic
Definition: avalon_bridge.vhd:83
avalon_bridge.s8_address
in s8_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:196
avalon_bridge.m3_readdata
in m3_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:92
avalon_bridge.m25_burstcount
out m25_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:578
avalon_bridge.m25_address
out m25_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:580
avalon_bridge.s25_writedata
in s25_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:569
avalon_bridge.s12_waitrequest
out s12_waitrequeststd_logic
Definition: avalon_bridge.vhd:279
avalon_bridge.m1_address
out m1_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:52
avalon_bridge.m8_writedata
out m8_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:205
avalon_bridge.s26_waitrequest
out s26_waitrequeststd_logic
Definition: avalon_bridge.vhd:587
avalon_bridge.s28_byteenable
in s28_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:639
avalon_bridge.m19_write
out m19_writestd_logic
Definition: avalon_bridge.vhd:449
avalon_bridge.m26_read
out m26_readstd_logic
Definition: avalon_bridge.vhd:604
avalon_bridge.s10_address
in s10_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:240
avalon_bridge.m14_writedata
out m14_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:337
avalon_bridge.m23_readdata
in m23_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:532
avalon_bridge.s23_address
in s23_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:526
avalon_bridge.m11_writedata
out m11_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:271
avalon_bridge.m20_byteenable
out m20_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:473
avalon_bridge.m7_readdata
in m7_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:180
avalon_bridge.s4_address
in s4_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:108
avalon_bridge.s18_address
in s18_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:416
avalon_bridge.s28_readdata
out s28_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:632
avalon_bridge.DATA_WIDTH
DATA_WIDTHinteger := 32
Definition: avalon_bridge.vhd:21
avalon_bridge.m26_write
out m26_writestd_logic
Definition: avalon_bridge.vhd:603
avalon_bridge.m7_burstcount
out m7_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:182
avalon_bridge.s28_burstcount
in s28_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:634
avalon_bridge.m14_write
out m14_writestd_logic
Definition: avalon_bridge.vhd:339
avalon_bridge.s2_address
in s2_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:64
avalon_bridge.s28_readdatavalid
out s28_readdatavalidstd_logic
Definition: avalon_bridge.vhd:633
avalon_bridge.m2_byteenable
out m2_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:77
avalon_bridge.s22_write
in s22_writestd_logic
Definition: avalon_bridge.vhd:505
avalon_bridge.m2_readdata
in m2_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:70
avalon_bridge.s14_address
in s14_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:328
avalon_bridge.s15_write
in s15_writestd_logic
Definition: avalon_bridge.vhd:351
avalon_bridge.m20_readdata
in m20_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:466
avalon_bridge.s25_byteenable
in s25_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:573
avalon_bridge.s16_waitrequest
out s16_waitrequeststd_logic
Definition: avalon_bridge.vhd:367
avalon_bridge.s4_readdata
out s4_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:104
avalon_bridge.m8_address
out m8_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:206
avalon_bridge.s17_address
in s17_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:394
avalon_bridge.s5_readdatavalid
out s5_readdatavalidstd_logic
Definition: avalon_bridge.vhd:127
avalon_bridge.s22_read
in s22_readstd_logic
Definition: avalon_bridge.vhd:506
avalon_bridge.m21_writedata
out m21_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:491
avalon_bridge.m9_debugaccess
out m9_debugaccessstd_logic
Definition: avalon_bridge.vhd:232
avalon_bridge.m29_burstcount
out m29_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:666
avalon_bridge.m23_address
out m23_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:536
avalon_bridge.m21_read
out m21_readstd_logic
Definition: avalon_bridge.vhd:494
avalon_bridge.s10_readdatavalid
out s10_readdatavalidstd_logic
Definition: avalon_bridge.vhd:237
avalon_bridge.s27_read
in s27_readstd_logic
Definition: avalon_bridge.vhd:616
avalon_bridge.s9_byteenable
in s9_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:221
avalon_bridge.m19_readdata
in m19_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:444
avalon_bridge.s25_address
in s25_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:570
avalon_bridge.s19_readdata
out s19_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:434
avalon_bridge.s3_readdata
out s3_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:82
avalon_bridge.s24_readdata
out s24_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:544
avalon_bridge.s12_byteenable
in s12_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:287
avalon_bridge.m6_address
out m6_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:162
avalon_bridge.m5_waitrequest
in m5_waitrequeststd_logic
Definition: avalon_bridge.vhd:135
avalon_bridge.m17_address
out m17_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:404
avalon_bridge.s26_readdata
out s26_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:588
avalon_bridge.m28_write
out m28_writestd_logic
Definition: avalon_bridge.vhd:647
avalon_bridge.s31_readdatavalid
out s31_readdatavalidstd_logic
Definition: avalon_bridge.vhd:699
avalon_bridge.s18_writedata
in s18_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:415
avalon_bridge.m28_readdata
in m28_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:642
avalon_bridge.s21_read
in s21_readstd_logic
Definition: avalon_bridge.vhd:484
avalon_bridge.m27_burstcount
out m27_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:622
avalon_bridge.s14_debugaccess
in s14_debugaccessstd_logic
Definition: avalon_bridge.vhd:332
avalon_bridge.m17_write
out m17_writestd_logic
Definition: avalon_bridge.vhd:405
avalon_bridge.s15_read
in s15_readstd_logic
Definition: avalon_bridge.vhd:352
avalon_bridge.s7_debugaccess
in s7_debugaccessstd_logic
Definition: avalon_bridge.vhd:178
avalon_bridge.s20_writedata
in s20_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:459
avalon_bridge.m4_readdata
in m4_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:114
avalon_bridge.m21_burstcount
out m21_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:490
avalon_bridge.s11_byteenable
in s11_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:265
avalon_bridge.s32_address
in s32_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:724
avalon_bridge.s23_burstcount
in s23_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:524
avalon_bridge.m15_readdatavalid
in m15_readdatavalidstd_logic
Definition: avalon_bridge.vhd:357
avalon_bridge.s5_writedata
in s5_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:129
avalon_bridge.m15_waitrequest
in m15_waitrequeststd_logic
Definition: avalon_bridge.vhd:355
avalon_bridge.s31_read
in s31_readstd_logic
Definition: avalon_bridge.vhd:704
avalon_bridge.s1_debugaccess
in s1_debugaccessstd_logic
Definition: avalon_bridge.vhd:46
avalon_bridge.s20_readdata
out s20_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:456
avalon_bridge.DEVICE_FAMILY
DEVICE_FAMILYstring
Definition: avalon_bridge.vhd:26
avalon_bridge.s23_readdatavalid
out s23_readdatavalidstd_logic
Definition: avalon_bridge.vhd:523
avalon_bridge.m22_readdata
in m22_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:510
avalon_bridge.m6_writedata
out m6_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:161
avalon_bridge.s19_writedata
in s19_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:437
avalon_bridge.m18_byteenable
out m18_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_bridge.vhd:429
avalon_bridge.s14_write
in s14_writestd_logic
Definition: avalon_bridge.vhd:329
Generated by   doxygen 1.8.17