GeMRTOS
Generics | Ports | Libraries | Use Clauses
avalon_bridge Entity Reference

Entities

AM1  architecture
 

Libraries

ieee 
altera_mf 

Use Clauses

std_logic_1164 
std_logic_unsigned 
numeric_std 
all  

Generics

NProcessors  integer
DATA_WIDTH  integer := 32
ADDRESS_WIDTH  integer := 32
BURSTCOUNT_WIDTH  integer := 1
BYTEEN_WIDTH  integer := 4
DEVICE_FAMILY  string

Ports

clk   in   std_logic
reset   in   std_logic
s1_waitrequest   out   std_logic
s1_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s1_readdatavalid   out   std_logic
s1_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s1_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s1_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s1_write   in   std_logic
s1_read   in   std_logic
s1_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s1_debugaccess   in   std_logic
m1_waitrequest   in   std_logic
m1_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m1_readdatavalid   in   std_logic
m1_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m1_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m1_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m1_write   out   std_logic
m1_read   out   std_logic
m1_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m1_debugaccess   out   std_logic
s2_waitrequest   out   std_logic
s2_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s2_readdatavalid   out   std_logic
s2_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s2_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s2_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s2_write   in   std_logic
s2_read   in   std_logic
s2_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s2_debugaccess   in   std_logic
m2_waitrequest   in   std_logic
m2_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m2_readdatavalid   in   std_logic
m2_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m2_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m2_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m2_write   out   std_logic
m2_read   out   std_logic
m2_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m2_debugaccess   out   std_logic
s3_waitrequest   out   std_logic
s3_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s3_readdatavalid   out   std_logic
s3_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s3_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s3_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s3_write   in   std_logic
s3_read   in   std_logic
s3_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s3_debugaccess   in   std_logic
m3_waitrequest   in   std_logic
m3_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m3_readdatavalid   in   std_logic
m3_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m3_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m3_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m3_write   out   std_logic
m3_read   out   std_logic
m3_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m3_debugaccess   out   std_logic
s4_waitrequest   out   std_logic
s4_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s4_readdatavalid   out   std_logic
s4_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s4_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s4_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s4_write   in   std_logic
s4_read   in   std_logic
s4_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s4_debugaccess   in   std_logic
m4_waitrequest   in   std_logic
m4_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m4_readdatavalid   in   std_logic
m4_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m4_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m4_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m4_write   out   std_logic
m4_read   out   std_logic
m4_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m4_debugaccess   out   std_logic
s5_waitrequest   out   std_logic
s5_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s5_readdatavalid   out   std_logic
s5_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s5_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s5_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s5_write   in   std_logic
s5_read   in   std_logic
s5_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s5_debugaccess   in   std_logic
m5_waitrequest   in   std_logic
m5_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m5_readdatavalid   in   std_logic
m5_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m5_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m5_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m5_write   out   std_logic
m5_read   out   std_logic
m5_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m5_debugaccess   out   std_logic
s6_waitrequest   out   std_logic
s6_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s6_readdatavalid   out   std_logic
s6_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s6_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s6_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s6_write   in   std_logic
s6_read   in   std_logic
s6_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s6_debugaccess   in   std_logic
m6_waitrequest   in   std_logic
m6_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m6_readdatavalid   in   std_logic
m6_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m6_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m6_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m6_write   out   std_logic
m6_read   out   std_logic
m6_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m6_debugaccess   out   std_logic
s7_waitrequest   out   std_logic
s7_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s7_readdatavalid   out   std_logic
s7_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s7_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s7_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s7_write   in   std_logic
s7_read   in   std_logic
s7_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s7_debugaccess   in   std_logic
m7_waitrequest   in   std_logic
m7_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m7_readdatavalid   in   std_logic
m7_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m7_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m7_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m7_write   out   std_logic
m7_read   out   std_logic
m7_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m7_debugaccess   out   std_logic
s8_waitrequest   out   std_logic
s8_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s8_readdatavalid   out   std_logic
s8_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s8_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s8_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s8_write   in   std_logic
s8_read   in   std_logic
s8_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s8_debugaccess   in   std_logic
m8_waitrequest   in   std_logic
m8_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m8_readdatavalid   in   std_logic
m8_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m8_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m8_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m8_write   out   std_logic
m8_read   out   std_logic
m8_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m8_debugaccess   out   std_logic
s9_waitrequest   out   std_logic
s9_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s9_readdatavalid   out   std_logic
s9_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s9_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s9_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s9_write   in   std_logic
s9_read   in   std_logic
s9_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s9_debugaccess   in   std_logic
m9_waitrequest   in   std_logic
m9_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m9_readdatavalid   in   std_logic
m9_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m9_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m9_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m9_write   out   std_logic
m9_read   out   std_logic
m9_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m9_debugaccess   out   std_logic
s10_waitrequest   out   std_logic
s10_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s10_readdatavalid   out   std_logic
s10_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s10_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s10_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s10_write   in   std_logic
s10_read   in   std_logic
s10_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s10_debugaccess   in   std_logic
m10_waitrequest   in   std_logic
m10_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m10_readdatavalid   in   std_logic
m10_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m10_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m10_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m10_write   out   std_logic
m10_read   out   std_logic
m10_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m10_debugaccess   out   std_logic
s11_waitrequest   out   std_logic
s11_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s11_readdatavalid   out   std_logic
s11_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s11_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s11_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s11_write   in   std_logic
s11_read   in   std_logic
s11_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s11_debugaccess   in   std_logic
m11_waitrequest   in   std_logic
m11_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m11_readdatavalid   in   std_logic
m11_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m11_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m11_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m11_write   out   std_logic
m11_read   out   std_logic
m11_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m11_debugaccess   out   std_logic
s12_waitrequest   out   std_logic
s12_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s12_readdatavalid   out   std_logic
s12_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s12_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s12_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s12_write   in   std_logic
s12_read   in   std_logic
s12_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s12_debugaccess   in   std_logic
m12_waitrequest   in   std_logic
m12_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m12_readdatavalid   in   std_logic
m12_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m12_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m12_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m12_write   out   std_logic
m12_read   out   std_logic
m12_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m12_debugaccess   out   std_logic
s13_waitrequest   out   std_logic
s13_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s13_readdatavalid   out   std_logic
s13_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s13_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s13_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s13_write   in   std_logic
s13_read   in   std_logic
s13_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s13_debugaccess   in   std_logic
m13_waitrequest   in   std_logic
m13_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m13_readdatavalid   in   std_logic
m13_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m13_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m13_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m13_write   out   std_logic
m13_read   out   std_logic
m13_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m13_debugaccess   out   std_logic
s14_waitrequest   out   std_logic
s14_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s14_readdatavalid   out   std_logic
s14_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s14_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s14_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s14_write   in   std_logic
s14_read   in   std_logic
s14_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s14_debugaccess   in   std_logic
m14_waitrequest   in   std_logic
m14_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m14_readdatavalid   in   std_logic
m14_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m14_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m14_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m14_write   out   std_logic
m14_read   out   std_logic
m14_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m14_debugaccess   out   std_logic
s15_waitrequest   out   std_logic
s15_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s15_readdatavalid   out   std_logic
s15_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s15_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s15_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s15_write   in   std_logic
s15_read   in   std_logic
s15_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s15_debugaccess   in   std_logic
m15_waitrequest   in   std_logic
m15_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m15_readdatavalid   in   std_logic
m15_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m15_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m15_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m15_write   out   std_logic
m15_read   out   std_logic
m15_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m15_debugaccess   out   std_logic
s16_waitrequest   out   std_logic
s16_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s16_readdatavalid   out   std_logic
s16_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s16_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s16_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s16_write   in   std_logic
s16_read   in   std_logic
s16_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s16_debugaccess   in   std_logic
m16_waitrequest   in   std_logic
m16_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m16_readdatavalid   in   std_logic
m16_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m16_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m16_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m16_write   out   std_logic
m16_read   out   std_logic
m16_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m16_debugaccess   out   std_logic
s17_waitrequest   out   std_logic
s17_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s17_readdatavalid   out   std_logic
s17_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s17_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s17_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s17_write   in   std_logic
s17_read   in   std_logic
s17_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s17_debugaccess   in   std_logic
m17_waitrequest   in   std_logic
m17_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m17_readdatavalid   in   std_logic
m17_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m17_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m17_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m17_write   out   std_logic
m17_read   out   std_logic
m17_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m17_debugaccess   out   std_logic
s18_waitrequest   out   std_logic
s18_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s18_readdatavalid   out   std_logic
s18_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s18_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s18_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s18_write   in   std_logic
s18_read   in   std_logic
s18_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s18_debugaccess   in   std_logic
m18_waitrequest   in   std_logic
m18_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m18_readdatavalid   in   std_logic
m18_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m18_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m18_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m18_write   out   std_logic
m18_read   out   std_logic
m18_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m18_debugaccess   out   std_logic
s19_waitrequest   out   std_logic
s19_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s19_readdatavalid   out   std_logic
s19_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s19_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s19_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s19_write   in   std_logic
s19_read   in   std_logic
s19_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s19_debugaccess   in   std_logic
m19_waitrequest   in   std_logic
m19_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m19_readdatavalid   in   std_logic
m19_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m19_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m19_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m19_write   out   std_logic
m19_read   out   std_logic
m19_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m19_debugaccess   out   std_logic
s20_waitrequest   out   std_logic
s20_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s20_readdatavalid   out   std_logic
s20_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s20_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s20_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s20_write   in   std_logic
s20_read   in   std_logic
s20_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s20_debugaccess   in   std_logic
m20_waitrequest   in   std_logic
m20_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m20_readdatavalid   in   std_logic
m20_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m20_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m20_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m20_write   out   std_logic
m20_read   out   std_logic
m20_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m20_debugaccess   out   std_logic
s21_waitrequest   out   std_logic
s21_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s21_readdatavalid   out   std_logic
s21_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s21_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s21_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s21_write   in   std_logic
s21_read   in   std_logic
s21_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s21_debugaccess   in   std_logic
m21_waitrequest   in   std_logic
m21_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m21_readdatavalid   in   std_logic
m21_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m21_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m21_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m21_write   out   std_logic
m21_read   out   std_logic
m21_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m21_debugaccess   out   std_logic
s22_waitrequest   out   std_logic
s22_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s22_readdatavalid   out   std_logic
s22_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s22_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s22_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s22_write   in   std_logic
s22_read   in   std_logic
s22_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s22_debugaccess   in   std_logic
m22_waitrequest   in   std_logic
m22_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m22_readdatavalid   in   std_logic
m22_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m22_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m22_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m22_write   out   std_logic
m22_read   out   std_logic
m22_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m22_debugaccess   out   std_logic
s23_waitrequest   out   std_logic
s23_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s23_readdatavalid   out   std_logic
s23_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s23_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s23_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s23_write   in   std_logic
s23_read   in   std_logic
s23_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s23_debugaccess   in   std_logic
m23_waitrequest   in   std_logic
m23_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m23_readdatavalid   in   std_logic
m23_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m23_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m23_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m23_write   out   std_logic
m23_read   out   std_logic
m23_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m23_debugaccess   out   std_logic
s24_waitrequest   out   std_logic
s24_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s24_readdatavalid   out   std_logic
s24_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s24_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s24_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s24_write   in   std_logic
s24_read   in   std_logic
s24_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s24_debugaccess   in   std_logic
m24_waitrequest   in   std_logic
m24_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m24_readdatavalid   in   std_logic
m24_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m24_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m24_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m24_write   out   std_logic
m24_read   out   std_logic
m24_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m24_debugaccess   out   std_logic
s25_waitrequest   out   std_logic
s25_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s25_readdatavalid   out   std_logic
s25_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s25_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s25_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s25_write   in   std_logic
s25_read   in   std_logic
s25_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s25_debugaccess   in   std_logic
m25_waitrequest   in   std_logic
m25_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m25_readdatavalid   in   std_logic
m25_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m25_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m25_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m25_write   out   std_logic
m25_read   out   std_logic
m25_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m25_debugaccess   out   std_logic
s26_waitrequest   out   std_logic
s26_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s26_readdatavalid   out   std_logic
s26_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s26_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s26_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s26_write   in   std_logic
s26_read   in   std_logic
s26_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s26_debugaccess   in   std_logic
m26_waitrequest   in   std_logic
m26_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m26_readdatavalid   in   std_logic
m26_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m26_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m26_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m26_write   out   std_logic
m26_read   out   std_logic
m26_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m26_debugaccess   out   std_logic
s27_waitrequest   out   std_logic
s27_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s27_readdatavalid   out   std_logic
s27_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s27_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s27_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s27_write   in   std_logic
s27_read   in   std_logic
s27_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s27_debugaccess   in   std_logic
m27_waitrequest   in   std_logic
m27_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m27_readdatavalid   in   std_logic
m27_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m27_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m27_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m27_write   out   std_logic
m27_read   out   std_logic
m27_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m27_debugaccess   out   std_logic
s28_waitrequest   out   std_logic
s28_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s28_readdatavalid   out   std_logic
s28_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s28_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s28_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s28_write   in   std_logic
s28_read   in   std_logic
s28_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s28_debugaccess   in   std_logic
m28_waitrequest   in   std_logic
m28_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m28_readdatavalid   in   std_logic
m28_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m28_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m28_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m28_write   out   std_logic
m28_read   out   std_logic
m28_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m28_debugaccess   out   std_logic
s29_waitrequest   out   std_logic
s29_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s29_readdatavalid   out   std_logic
s29_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s29_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s29_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s29_write   in   std_logic
s29_read   in   std_logic
s29_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s29_debugaccess   in   std_logic
m29_waitrequest   in   std_logic
m29_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m29_readdatavalid   in   std_logic
m29_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m29_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m29_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m29_write   out   std_logic
m29_read   out   std_logic
m29_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m29_debugaccess   out   std_logic
s30_waitrequest   out   std_logic
s30_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s30_readdatavalid   out   std_logic
s30_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s30_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s30_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s30_write   in   std_logic
s30_read   in   std_logic
s30_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s30_debugaccess   in   std_logic
m30_waitrequest   in   std_logic
m30_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m30_readdatavalid   in   std_logic
m30_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m30_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m30_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m30_write   out   std_logic
m30_read   out   std_logic
m30_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m30_debugaccess   out   std_logic
s31_waitrequest   out   std_logic
s31_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s31_readdatavalid   out   std_logic
s31_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s31_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s31_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s31_write   in   std_logic
s31_read   in   std_logic
s31_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s31_debugaccess   in   std_logic
m31_waitrequest   in   std_logic
m31_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m31_readdatavalid   in   std_logic
m31_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m31_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m31_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m31_write   out   std_logic
m31_read   out   std_logic
m31_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m31_debugaccess   out   std_logic
s32_waitrequest   out   std_logic
s32_readdata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s32_readdatavalid   out   std_logic
s32_burstcount   in   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
s32_writedata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
s32_address   in   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
s32_write   in   std_logic
s32_read   in   std_logic
s32_byteenable   in   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
s32_debugaccess   in   std_logic
m32_waitrequest   in   std_logic
m32_readdata   in   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m32_readdatavalid   in   std_logic
m32_burstcount   out   std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
m32_writedata   out   std_logic_vector ( DATA_WIDTH - 1 downto 0 )
m32_address   out   std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
m32_write   out   std_logic
m32_read   out   std_logic
m32_byteenable   out   std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
m32_debugaccess   out   std_logic

Detailed Description

Definition at line 16 of file avalon_bridge.vhd.

Field Documentation

◆  all

all
use clause

Definition at line 12 of file avalon_bridge.vhd.

◆ ADDRESS_WIDTH

ADDRESS_WIDTH integer := 32
Generic

Definition at line 22 of file avalon_bridge.vhd.

◆ altera_mf

altera_mf
Library

Definition at line 11 of file avalon_bridge.vhd.

◆ BURSTCOUNT_WIDTH

BURSTCOUNT_WIDTH integer := 1
Generic

Definition at line 23 of file avalon_bridge.vhd.

◆ BYTEEN_WIDTH

BYTEEN_WIDTH integer := 4
Generic

Definition at line 24 of file avalon_bridge.vhd.

◆ clk

clk in std_logic
Port

Definition at line 29 of file avalon_bridge.vhd.

◆ DATA_WIDTH

DATA_WIDTH integer := 32
Generic

Definition at line 21 of file avalon_bridge.vhd.

◆ DEVICE_FAMILY

DEVICE_FAMILY string
Generic

Definition at line 26 of file avalon_bridge.vhd.

◆ ieee

ieee
Library

Definition at line 6 of file avalon_bridge.vhd.

◆ m10_address

m10_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 250 of file avalon_bridge.vhd.

◆ m10_burstcount

m10_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 248 of file avalon_bridge.vhd.

◆ m10_byteenable

m10_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 253 of file avalon_bridge.vhd.

◆ m10_debugaccess

m10_debugaccess out std_logic
Port

Definition at line 254 of file avalon_bridge.vhd.

◆ m10_read

m10_read out std_logic
Port

Definition at line 252 of file avalon_bridge.vhd.

◆ m10_readdata

m10_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 246 of file avalon_bridge.vhd.

◆ m10_readdatavalid

m10_readdatavalid in std_logic
Port

Definition at line 247 of file avalon_bridge.vhd.

◆ m10_waitrequest

m10_waitrequest in std_logic
Port

Definition at line 245 of file avalon_bridge.vhd.

◆ m10_write

m10_write out std_logic
Port

Definition at line 251 of file avalon_bridge.vhd.

◆ m10_writedata

m10_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 249 of file avalon_bridge.vhd.

◆ m11_address

m11_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 272 of file avalon_bridge.vhd.

◆ m11_burstcount

m11_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 270 of file avalon_bridge.vhd.

◆ m11_byteenable

m11_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 275 of file avalon_bridge.vhd.

◆ m11_debugaccess

m11_debugaccess out std_logic
Port

Definition at line 276 of file avalon_bridge.vhd.

◆ m11_read

m11_read out std_logic
Port

Definition at line 274 of file avalon_bridge.vhd.

◆ m11_readdata

m11_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 268 of file avalon_bridge.vhd.

◆ m11_readdatavalid

m11_readdatavalid in std_logic
Port

Definition at line 269 of file avalon_bridge.vhd.

◆ m11_waitrequest

m11_waitrequest in std_logic
Port

Definition at line 267 of file avalon_bridge.vhd.

◆ m11_write

m11_write out std_logic
Port

Definition at line 273 of file avalon_bridge.vhd.

◆ m11_writedata

m11_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 271 of file avalon_bridge.vhd.

◆ m12_address

m12_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 294 of file avalon_bridge.vhd.

◆ m12_burstcount

m12_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 292 of file avalon_bridge.vhd.

◆ m12_byteenable

m12_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 297 of file avalon_bridge.vhd.

◆ m12_debugaccess

m12_debugaccess out std_logic
Port

Definition at line 298 of file avalon_bridge.vhd.

◆ m12_read

m12_read out std_logic
Port

Definition at line 296 of file avalon_bridge.vhd.

◆ m12_readdata

m12_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 290 of file avalon_bridge.vhd.

◆ m12_readdatavalid

m12_readdatavalid in std_logic
Port

Definition at line 291 of file avalon_bridge.vhd.

◆ m12_waitrequest

m12_waitrequest in std_logic
Port

Definition at line 289 of file avalon_bridge.vhd.

◆ m12_write

m12_write out std_logic
Port

Definition at line 295 of file avalon_bridge.vhd.

◆ m12_writedata

m12_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 293 of file avalon_bridge.vhd.

◆ m13_address

m13_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 316 of file avalon_bridge.vhd.

◆ m13_burstcount

m13_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 314 of file avalon_bridge.vhd.

◆ m13_byteenable

m13_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 319 of file avalon_bridge.vhd.

◆ m13_debugaccess

m13_debugaccess out std_logic
Port

Definition at line 320 of file avalon_bridge.vhd.

◆ m13_read

m13_read out std_logic
Port

Definition at line 318 of file avalon_bridge.vhd.

◆ m13_readdata

m13_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 312 of file avalon_bridge.vhd.

◆ m13_readdatavalid

m13_readdatavalid in std_logic
Port

Definition at line 313 of file avalon_bridge.vhd.

◆ m13_waitrequest

m13_waitrequest in std_logic
Port

Definition at line 311 of file avalon_bridge.vhd.

◆ m13_write

m13_write out std_logic
Port

Definition at line 317 of file avalon_bridge.vhd.

◆ m13_writedata

m13_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 315 of file avalon_bridge.vhd.

◆ m14_address

m14_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 338 of file avalon_bridge.vhd.

◆ m14_burstcount

m14_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 336 of file avalon_bridge.vhd.

◆ m14_byteenable

m14_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 341 of file avalon_bridge.vhd.

◆ m14_debugaccess

m14_debugaccess out std_logic
Port

Definition at line 342 of file avalon_bridge.vhd.

◆ m14_read

m14_read out std_logic
Port

Definition at line 340 of file avalon_bridge.vhd.

◆ m14_readdata

m14_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 334 of file avalon_bridge.vhd.

◆ m14_readdatavalid

m14_readdatavalid in std_logic
Port

Definition at line 335 of file avalon_bridge.vhd.

◆ m14_waitrequest

m14_waitrequest in std_logic
Port

Definition at line 333 of file avalon_bridge.vhd.

◆ m14_write

m14_write out std_logic
Port

Definition at line 339 of file avalon_bridge.vhd.

◆ m14_writedata

m14_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 337 of file avalon_bridge.vhd.

◆ m15_address

m15_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 360 of file avalon_bridge.vhd.

◆ m15_burstcount

m15_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 358 of file avalon_bridge.vhd.

◆ m15_byteenable

m15_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 363 of file avalon_bridge.vhd.

◆ m15_debugaccess

m15_debugaccess out std_logic
Port

Definition at line 364 of file avalon_bridge.vhd.

◆ m15_read

m15_read out std_logic
Port

Definition at line 362 of file avalon_bridge.vhd.

◆ m15_readdata

m15_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 356 of file avalon_bridge.vhd.

◆ m15_readdatavalid

m15_readdatavalid in std_logic
Port

Definition at line 357 of file avalon_bridge.vhd.

◆ m15_waitrequest

m15_waitrequest in std_logic
Port

Definition at line 355 of file avalon_bridge.vhd.

◆ m15_write

m15_write out std_logic
Port

Definition at line 361 of file avalon_bridge.vhd.

◆ m15_writedata

m15_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 359 of file avalon_bridge.vhd.

◆ m16_address

m16_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 382 of file avalon_bridge.vhd.

◆ m16_burstcount

m16_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 380 of file avalon_bridge.vhd.

◆ m16_byteenable

m16_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 385 of file avalon_bridge.vhd.

◆ m16_debugaccess

m16_debugaccess out std_logic
Port

Definition at line 386 of file avalon_bridge.vhd.

◆ m16_read

m16_read out std_logic
Port

Definition at line 384 of file avalon_bridge.vhd.

◆ m16_readdata

m16_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 378 of file avalon_bridge.vhd.

◆ m16_readdatavalid

m16_readdatavalid in std_logic
Port

Definition at line 379 of file avalon_bridge.vhd.

◆ m16_waitrequest

m16_waitrequest in std_logic
Port

Definition at line 377 of file avalon_bridge.vhd.

◆ m16_write

m16_write out std_logic
Port

Definition at line 383 of file avalon_bridge.vhd.

◆ m16_writedata

m16_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 381 of file avalon_bridge.vhd.

◆ m17_address

m17_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 404 of file avalon_bridge.vhd.

◆ m17_burstcount

m17_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 402 of file avalon_bridge.vhd.

◆ m17_byteenable

m17_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 407 of file avalon_bridge.vhd.

◆ m17_debugaccess

m17_debugaccess out std_logic
Port

Definition at line 408 of file avalon_bridge.vhd.

◆ m17_read

m17_read out std_logic
Port

Definition at line 406 of file avalon_bridge.vhd.

◆ m17_readdata

m17_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 400 of file avalon_bridge.vhd.

◆ m17_readdatavalid

m17_readdatavalid in std_logic
Port

Definition at line 401 of file avalon_bridge.vhd.

◆ m17_waitrequest

m17_waitrequest in std_logic
Port

Definition at line 399 of file avalon_bridge.vhd.

◆ m17_write

m17_write out std_logic
Port

Definition at line 405 of file avalon_bridge.vhd.

◆ m17_writedata

m17_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 403 of file avalon_bridge.vhd.

◆ m18_address

m18_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 426 of file avalon_bridge.vhd.

◆ m18_burstcount

m18_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 424 of file avalon_bridge.vhd.

◆ m18_byteenable

m18_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 429 of file avalon_bridge.vhd.

◆ m18_debugaccess

m18_debugaccess out std_logic
Port

Definition at line 430 of file avalon_bridge.vhd.

◆ m18_read

m18_read out std_logic
Port

Definition at line 428 of file avalon_bridge.vhd.

◆ m18_readdata

m18_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 422 of file avalon_bridge.vhd.

◆ m18_readdatavalid

m18_readdatavalid in std_logic
Port

Definition at line 423 of file avalon_bridge.vhd.

◆ m18_waitrequest

m18_waitrequest in std_logic
Port

Definition at line 421 of file avalon_bridge.vhd.

◆ m18_write

m18_write out std_logic
Port

Definition at line 427 of file avalon_bridge.vhd.

◆ m18_writedata

m18_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 425 of file avalon_bridge.vhd.

◆ m19_address

m19_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 448 of file avalon_bridge.vhd.

◆ m19_burstcount

m19_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 446 of file avalon_bridge.vhd.

◆ m19_byteenable

m19_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 451 of file avalon_bridge.vhd.

◆ m19_debugaccess

m19_debugaccess out std_logic
Port

Definition at line 452 of file avalon_bridge.vhd.

◆ m19_read

m19_read out std_logic
Port

Definition at line 450 of file avalon_bridge.vhd.

◆ m19_readdata

m19_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 444 of file avalon_bridge.vhd.

◆ m19_readdatavalid

m19_readdatavalid in std_logic
Port

Definition at line 445 of file avalon_bridge.vhd.

◆ m19_waitrequest

m19_waitrequest in std_logic
Port

Definition at line 443 of file avalon_bridge.vhd.

◆ m19_write

m19_write out std_logic
Port

Definition at line 449 of file avalon_bridge.vhd.

◆ m19_writedata

m19_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 447 of file avalon_bridge.vhd.

◆ m1_address

m1_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 52 of file avalon_bridge.vhd.

◆ m1_burstcount

m1_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 50 of file avalon_bridge.vhd.

◆ m1_byteenable

m1_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 55 of file avalon_bridge.vhd.

◆ m1_debugaccess

m1_debugaccess out std_logic
Port

Definition at line 56 of file avalon_bridge.vhd.

◆ m1_read

m1_read out std_logic
Port

Definition at line 54 of file avalon_bridge.vhd.

◆ m1_readdata

m1_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 48 of file avalon_bridge.vhd.

◆ m1_readdatavalid

m1_readdatavalid in std_logic
Port

Definition at line 49 of file avalon_bridge.vhd.

◆ m1_waitrequest

m1_waitrequest in std_logic
Port

Definition at line 47 of file avalon_bridge.vhd.

◆ m1_write

m1_write out std_logic
Port

Definition at line 53 of file avalon_bridge.vhd.

◆ m1_writedata

m1_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 51 of file avalon_bridge.vhd.

◆ m20_address

m20_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 470 of file avalon_bridge.vhd.

◆ m20_burstcount

m20_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 468 of file avalon_bridge.vhd.

◆ m20_byteenable

m20_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 473 of file avalon_bridge.vhd.

◆ m20_debugaccess

m20_debugaccess out std_logic
Port

Definition at line 474 of file avalon_bridge.vhd.

◆ m20_read

m20_read out std_logic
Port

Definition at line 472 of file avalon_bridge.vhd.

◆ m20_readdata

m20_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 466 of file avalon_bridge.vhd.

◆ m20_readdatavalid

m20_readdatavalid in std_logic
Port

Definition at line 467 of file avalon_bridge.vhd.

◆ m20_waitrequest

m20_waitrequest in std_logic
Port

Definition at line 465 of file avalon_bridge.vhd.

◆ m20_write

m20_write out std_logic
Port

Definition at line 471 of file avalon_bridge.vhd.

◆ m20_writedata

m20_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 469 of file avalon_bridge.vhd.

◆ m21_address

m21_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 492 of file avalon_bridge.vhd.

◆ m21_burstcount

m21_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 490 of file avalon_bridge.vhd.

◆ m21_byteenable

m21_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 495 of file avalon_bridge.vhd.

◆ m21_debugaccess

m21_debugaccess out std_logic
Port

Definition at line 496 of file avalon_bridge.vhd.

◆ m21_read

m21_read out std_logic
Port

Definition at line 494 of file avalon_bridge.vhd.

◆ m21_readdata

m21_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 488 of file avalon_bridge.vhd.

◆ m21_readdatavalid

m21_readdatavalid in std_logic
Port

Definition at line 489 of file avalon_bridge.vhd.

◆ m21_waitrequest

m21_waitrequest in std_logic
Port

Definition at line 487 of file avalon_bridge.vhd.

◆ m21_write

m21_write out std_logic
Port

Definition at line 493 of file avalon_bridge.vhd.

◆ m21_writedata

m21_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 491 of file avalon_bridge.vhd.

◆ m22_address

m22_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 514 of file avalon_bridge.vhd.

◆ m22_burstcount

m22_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 512 of file avalon_bridge.vhd.

◆ m22_byteenable

m22_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 517 of file avalon_bridge.vhd.

◆ m22_debugaccess

m22_debugaccess out std_logic
Port

Definition at line 518 of file avalon_bridge.vhd.

◆ m22_read

m22_read out std_logic
Port

Definition at line 516 of file avalon_bridge.vhd.

◆ m22_readdata

m22_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 510 of file avalon_bridge.vhd.

◆ m22_readdatavalid

m22_readdatavalid in std_logic
Port

Definition at line 511 of file avalon_bridge.vhd.

◆ m22_waitrequest

m22_waitrequest in std_logic
Port

Definition at line 509 of file avalon_bridge.vhd.

◆ m22_write

m22_write out std_logic
Port

Definition at line 515 of file avalon_bridge.vhd.

◆ m22_writedata

m22_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 513 of file avalon_bridge.vhd.

◆ m23_address

m23_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 536 of file avalon_bridge.vhd.

◆ m23_burstcount

m23_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 534 of file avalon_bridge.vhd.

◆ m23_byteenable

m23_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 539 of file avalon_bridge.vhd.

◆ m23_debugaccess

m23_debugaccess out std_logic
Port

Definition at line 540 of file avalon_bridge.vhd.

◆ m23_read

m23_read out std_logic
Port

Definition at line 538 of file avalon_bridge.vhd.

◆ m23_readdata

m23_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 532 of file avalon_bridge.vhd.

◆ m23_readdatavalid

m23_readdatavalid in std_logic
Port

Definition at line 533 of file avalon_bridge.vhd.

◆ m23_waitrequest

m23_waitrequest in std_logic
Port

Definition at line 531 of file avalon_bridge.vhd.

◆ m23_write

m23_write out std_logic
Port

Definition at line 537 of file avalon_bridge.vhd.

◆ m23_writedata

m23_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 535 of file avalon_bridge.vhd.

◆ m24_address

m24_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 558 of file avalon_bridge.vhd.

◆ m24_burstcount

m24_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 556 of file avalon_bridge.vhd.

◆ m24_byteenable

m24_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 561 of file avalon_bridge.vhd.

◆ m24_debugaccess

m24_debugaccess out std_logic
Port

Definition at line 562 of file avalon_bridge.vhd.

◆ m24_read

m24_read out std_logic
Port

Definition at line 560 of file avalon_bridge.vhd.

◆ m24_readdata

m24_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 554 of file avalon_bridge.vhd.

◆ m24_readdatavalid

m24_readdatavalid in std_logic
Port

Definition at line 555 of file avalon_bridge.vhd.

◆ m24_waitrequest

m24_waitrequest in std_logic
Port

Definition at line 553 of file avalon_bridge.vhd.

◆ m24_write

m24_write out std_logic
Port

Definition at line 559 of file avalon_bridge.vhd.

◆ m24_writedata

m24_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 557 of file avalon_bridge.vhd.

◆ m25_address

m25_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 580 of file avalon_bridge.vhd.

◆ m25_burstcount

m25_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 578 of file avalon_bridge.vhd.

◆ m25_byteenable

m25_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 583 of file avalon_bridge.vhd.

◆ m25_debugaccess

m25_debugaccess out std_logic
Port

Definition at line 584 of file avalon_bridge.vhd.

◆ m25_read

m25_read out std_logic
Port

Definition at line 582 of file avalon_bridge.vhd.

◆ m25_readdata

m25_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 576 of file avalon_bridge.vhd.

◆ m25_readdatavalid

m25_readdatavalid in std_logic
Port

Definition at line 577 of file avalon_bridge.vhd.

◆ m25_waitrequest

m25_waitrequest in std_logic
Port

Definition at line 575 of file avalon_bridge.vhd.

◆ m25_write

m25_write out std_logic
Port

Definition at line 581 of file avalon_bridge.vhd.

◆ m25_writedata

m25_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 579 of file avalon_bridge.vhd.

◆ m26_address

m26_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 602 of file avalon_bridge.vhd.

◆ m26_burstcount

m26_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 600 of file avalon_bridge.vhd.

◆ m26_byteenable

m26_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 605 of file avalon_bridge.vhd.

◆ m26_debugaccess

m26_debugaccess out std_logic
Port

Definition at line 606 of file avalon_bridge.vhd.

◆ m26_read

m26_read out std_logic
Port

Definition at line 604 of file avalon_bridge.vhd.

◆ m26_readdata

m26_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 598 of file avalon_bridge.vhd.

◆ m26_readdatavalid

m26_readdatavalid in std_logic
Port

Definition at line 599 of file avalon_bridge.vhd.

◆ m26_waitrequest

m26_waitrequest in std_logic
Port

Definition at line 597 of file avalon_bridge.vhd.

◆ m26_write

m26_write out std_logic
Port

Definition at line 603 of file avalon_bridge.vhd.

◆ m26_writedata

m26_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 601 of file avalon_bridge.vhd.

◆ m27_address

m27_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 624 of file avalon_bridge.vhd.

◆ m27_burstcount

m27_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 622 of file avalon_bridge.vhd.

◆ m27_byteenable

m27_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 627 of file avalon_bridge.vhd.

◆ m27_debugaccess

m27_debugaccess out std_logic
Port

Definition at line 628 of file avalon_bridge.vhd.

◆ m27_read

m27_read out std_logic
Port

Definition at line 626 of file avalon_bridge.vhd.

◆ m27_readdata

m27_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 620 of file avalon_bridge.vhd.

◆ m27_readdatavalid

m27_readdatavalid in std_logic
Port

Definition at line 621 of file avalon_bridge.vhd.

◆ m27_waitrequest

m27_waitrequest in std_logic
Port

Definition at line 619 of file avalon_bridge.vhd.

◆ m27_write

m27_write out std_logic
Port

Definition at line 625 of file avalon_bridge.vhd.

◆ m27_writedata

m27_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 623 of file avalon_bridge.vhd.

◆ m28_address

m28_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 646 of file avalon_bridge.vhd.

◆ m28_burstcount

m28_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 644 of file avalon_bridge.vhd.

◆ m28_byteenable

m28_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 649 of file avalon_bridge.vhd.

◆ m28_debugaccess

m28_debugaccess out std_logic
Port

Definition at line 650 of file avalon_bridge.vhd.

◆ m28_read

m28_read out std_logic
Port

Definition at line 648 of file avalon_bridge.vhd.

◆ m28_readdata

m28_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 642 of file avalon_bridge.vhd.

◆ m28_readdatavalid

m28_readdatavalid in std_logic
Port

Definition at line 643 of file avalon_bridge.vhd.

◆ m28_waitrequest

m28_waitrequest in std_logic
Port

Definition at line 641 of file avalon_bridge.vhd.

◆ m28_write

m28_write out std_logic
Port

Definition at line 647 of file avalon_bridge.vhd.

◆ m28_writedata

m28_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 645 of file avalon_bridge.vhd.

◆ m29_address

m29_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 668 of file avalon_bridge.vhd.

◆ m29_burstcount

m29_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 666 of file avalon_bridge.vhd.

◆ m29_byteenable

m29_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 671 of file avalon_bridge.vhd.

◆ m29_debugaccess

m29_debugaccess out std_logic
Port

Definition at line 672 of file avalon_bridge.vhd.

◆ m29_read

m29_read out std_logic
Port

Definition at line 670 of file avalon_bridge.vhd.

◆ m29_readdata

m29_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 664 of file avalon_bridge.vhd.

◆ m29_readdatavalid

m29_readdatavalid in std_logic
Port

Definition at line 665 of file avalon_bridge.vhd.

◆ m29_waitrequest

m29_waitrequest in std_logic
Port

Definition at line 663 of file avalon_bridge.vhd.

◆ m29_write

m29_write out std_logic
Port

Definition at line 669 of file avalon_bridge.vhd.

◆ m29_writedata

m29_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 667 of file avalon_bridge.vhd.

◆ m2_address

m2_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 74 of file avalon_bridge.vhd.

◆ m2_burstcount

m2_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 72 of file avalon_bridge.vhd.

◆ m2_byteenable

m2_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 77 of file avalon_bridge.vhd.

◆ m2_debugaccess

m2_debugaccess out std_logic
Port

Definition at line 78 of file avalon_bridge.vhd.

◆ m2_read

m2_read out std_logic
Port

Definition at line 76 of file avalon_bridge.vhd.

◆ m2_readdata

m2_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 70 of file avalon_bridge.vhd.

◆ m2_readdatavalid

m2_readdatavalid in std_logic
Port

Definition at line 71 of file avalon_bridge.vhd.

◆ m2_waitrequest

m2_waitrequest in std_logic
Port

Definition at line 69 of file avalon_bridge.vhd.

◆ m2_write

m2_write out std_logic
Port

Definition at line 75 of file avalon_bridge.vhd.

◆ m2_writedata

m2_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 73 of file avalon_bridge.vhd.

◆ m30_address

m30_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 690 of file avalon_bridge.vhd.

◆ m30_burstcount

m30_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 688 of file avalon_bridge.vhd.

◆ m30_byteenable

m30_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 693 of file avalon_bridge.vhd.

◆ m30_debugaccess

m30_debugaccess out std_logic
Port

Definition at line 694 of file avalon_bridge.vhd.

◆ m30_read

m30_read out std_logic
Port

Definition at line 692 of file avalon_bridge.vhd.

◆ m30_readdata

m30_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 686 of file avalon_bridge.vhd.

◆ m30_readdatavalid

m30_readdatavalid in std_logic
Port

Definition at line 687 of file avalon_bridge.vhd.

◆ m30_waitrequest

m30_waitrequest in std_logic
Port

Definition at line 685 of file avalon_bridge.vhd.

◆ m30_write

m30_write out std_logic
Port

Definition at line 691 of file avalon_bridge.vhd.

◆ m30_writedata

m30_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 689 of file avalon_bridge.vhd.

◆ m31_address

m31_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 712 of file avalon_bridge.vhd.

◆ m31_burstcount

m31_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 710 of file avalon_bridge.vhd.

◆ m31_byteenable

m31_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 715 of file avalon_bridge.vhd.

◆ m31_debugaccess

m31_debugaccess out std_logic
Port

Definition at line 716 of file avalon_bridge.vhd.

◆ m31_read

m31_read out std_logic
Port

Definition at line 714 of file avalon_bridge.vhd.

◆ m31_readdata

m31_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 708 of file avalon_bridge.vhd.

◆ m31_readdatavalid

m31_readdatavalid in std_logic
Port

Definition at line 709 of file avalon_bridge.vhd.

◆ m31_waitrequest

m31_waitrequest in std_logic
Port

Definition at line 707 of file avalon_bridge.vhd.

◆ m31_write

m31_write out std_logic
Port

Definition at line 713 of file avalon_bridge.vhd.

◆ m31_writedata

m31_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 711 of file avalon_bridge.vhd.

◆ m32_address

m32_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 734 of file avalon_bridge.vhd.

◆ m32_burstcount

m32_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 732 of file avalon_bridge.vhd.

◆ m32_byteenable

m32_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 737 of file avalon_bridge.vhd.

◆ m32_debugaccess

m32_debugaccess out std_logic
Port

Definition at line 740 of file avalon_bridge.vhd.

◆ m32_read

m32_read out std_logic
Port

Definition at line 736 of file avalon_bridge.vhd.

◆ m32_readdata

m32_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 730 of file avalon_bridge.vhd.

◆ m32_readdatavalid

m32_readdatavalid in std_logic
Port

Definition at line 731 of file avalon_bridge.vhd.

◆ m32_waitrequest

m32_waitrequest in std_logic
Port

Definition at line 729 of file avalon_bridge.vhd.

◆ m32_write

m32_write out std_logic
Port

Definition at line 735 of file avalon_bridge.vhd.

◆ m32_writedata

m32_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 733 of file avalon_bridge.vhd.

◆ m3_address

m3_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 96 of file avalon_bridge.vhd.

◆ m3_burstcount

m3_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 94 of file avalon_bridge.vhd.

◆ m3_byteenable

m3_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 99 of file avalon_bridge.vhd.

◆ m3_debugaccess

m3_debugaccess out std_logic
Port

Definition at line 100 of file avalon_bridge.vhd.

◆ m3_read

m3_read out std_logic
Port

Definition at line 98 of file avalon_bridge.vhd.

◆ m3_readdata

m3_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 92 of file avalon_bridge.vhd.

◆ m3_readdatavalid

m3_readdatavalid in std_logic
Port

Definition at line 93 of file avalon_bridge.vhd.

◆ m3_waitrequest

m3_waitrequest in std_logic
Port

Definition at line 91 of file avalon_bridge.vhd.

◆ m3_write

m3_write out std_logic
Port

Definition at line 97 of file avalon_bridge.vhd.

◆ m3_writedata

m3_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 95 of file avalon_bridge.vhd.

◆ m4_address

m4_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 118 of file avalon_bridge.vhd.

◆ m4_burstcount

m4_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 116 of file avalon_bridge.vhd.

◆ m4_byteenable

m4_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 121 of file avalon_bridge.vhd.

◆ m4_debugaccess

m4_debugaccess out std_logic
Port

Definition at line 122 of file avalon_bridge.vhd.

◆ m4_read

m4_read out std_logic
Port

Definition at line 120 of file avalon_bridge.vhd.

◆ m4_readdata

m4_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 114 of file avalon_bridge.vhd.

◆ m4_readdatavalid

m4_readdatavalid in std_logic
Port

Definition at line 115 of file avalon_bridge.vhd.

◆ m4_waitrequest

m4_waitrequest in std_logic
Port

Definition at line 113 of file avalon_bridge.vhd.

◆ m4_write

m4_write out std_logic
Port

Definition at line 119 of file avalon_bridge.vhd.

◆ m4_writedata

m4_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 117 of file avalon_bridge.vhd.

◆ m5_address

m5_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 140 of file avalon_bridge.vhd.

◆ m5_burstcount

m5_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 138 of file avalon_bridge.vhd.

◆ m5_byteenable

m5_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 143 of file avalon_bridge.vhd.

◆ m5_debugaccess

m5_debugaccess out std_logic
Port

Definition at line 144 of file avalon_bridge.vhd.

◆ m5_read

m5_read out std_logic
Port

Definition at line 142 of file avalon_bridge.vhd.

◆ m5_readdata

m5_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 136 of file avalon_bridge.vhd.

◆ m5_readdatavalid

m5_readdatavalid in std_logic
Port

Definition at line 137 of file avalon_bridge.vhd.

◆ m5_waitrequest

m5_waitrequest in std_logic
Port

Definition at line 135 of file avalon_bridge.vhd.

◆ m5_write

m5_write out std_logic
Port

Definition at line 141 of file avalon_bridge.vhd.

◆ m5_writedata

m5_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 139 of file avalon_bridge.vhd.

◆ m6_address

m6_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 162 of file avalon_bridge.vhd.

◆ m6_burstcount

m6_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 160 of file avalon_bridge.vhd.

◆ m6_byteenable

m6_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 165 of file avalon_bridge.vhd.

◆ m6_debugaccess

m6_debugaccess out std_logic
Port

Definition at line 166 of file avalon_bridge.vhd.

◆ m6_read

m6_read out std_logic
Port

Definition at line 164 of file avalon_bridge.vhd.

◆ m6_readdata

m6_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 158 of file avalon_bridge.vhd.

◆ m6_readdatavalid

m6_readdatavalid in std_logic
Port

Definition at line 159 of file avalon_bridge.vhd.

◆ m6_waitrequest

m6_waitrequest in std_logic
Port

Definition at line 157 of file avalon_bridge.vhd.

◆ m6_write

m6_write out std_logic
Port

Definition at line 163 of file avalon_bridge.vhd.

◆ m6_writedata

m6_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 161 of file avalon_bridge.vhd.

◆ m7_address

m7_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 184 of file avalon_bridge.vhd.

◆ m7_burstcount

m7_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 182 of file avalon_bridge.vhd.

◆ m7_byteenable

m7_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 187 of file avalon_bridge.vhd.

◆ m7_debugaccess

m7_debugaccess out std_logic
Port

Definition at line 188 of file avalon_bridge.vhd.

◆ m7_read

m7_read out std_logic
Port

Definition at line 186 of file avalon_bridge.vhd.

◆ m7_readdata

m7_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 180 of file avalon_bridge.vhd.

◆ m7_readdatavalid

m7_readdatavalid in std_logic
Port

Definition at line 181 of file avalon_bridge.vhd.

◆ m7_waitrequest

m7_waitrequest in std_logic
Port

Definition at line 179 of file avalon_bridge.vhd.

◆ m7_write

m7_write out std_logic
Port

Definition at line 185 of file avalon_bridge.vhd.

◆ m7_writedata

m7_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 183 of file avalon_bridge.vhd.

◆ m8_address

m8_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 206 of file avalon_bridge.vhd.

◆ m8_burstcount

m8_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 204 of file avalon_bridge.vhd.

◆ m8_byteenable

m8_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 209 of file avalon_bridge.vhd.

◆ m8_debugaccess

m8_debugaccess out std_logic
Port

Definition at line 210 of file avalon_bridge.vhd.

◆ m8_read

m8_read out std_logic
Port

Definition at line 208 of file avalon_bridge.vhd.

◆ m8_readdata

m8_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 202 of file avalon_bridge.vhd.

◆ m8_readdatavalid

m8_readdatavalid in std_logic
Port

Definition at line 203 of file avalon_bridge.vhd.

◆ m8_waitrequest

m8_waitrequest in std_logic
Port

Definition at line 201 of file avalon_bridge.vhd.

◆ m8_write

m8_write out std_logic
Port

Definition at line 207 of file avalon_bridge.vhd.

◆ m8_writedata

m8_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 205 of file avalon_bridge.vhd.

◆ m9_address

m9_address out std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 228 of file avalon_bridge.vhd.

◆ m9_burstcount

m9_burstcount out std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 226 of file avalon_bridge.vhd.

◆ m9_byteenable

m9_byteenable out std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 231 of file avalon_bridge.vhd.

◆ m9_debugaccess

m9_debugaccess out std_logic
Port

Definition at line 232 of file avalon_bridge.vhd.

◆ m9_read

m9_read out std_logic
Port

Definition at line 230 of file avalon_bridge.vhd.

◆ m9_readdata

m9_readdata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 224 of file avalon_bridge.vhd.

◆ m9_readdatavalid

m9_readdatavalid in std_logic
Port

Definition at line 225 of file avalon_bridge.vhd.

◆ m9_waitrequest

m9_waitrequest in std_logic
Port

Definition at line 223 of file avalon_bridge.vhd.

◆ m9_write

m9_write out std_logic
Port

Definition at line 229 of file avalon_bridge.vhd.

◆ m9_writedata

m9_writedata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 227 of file avalon_bridge.vhd.

◆ NProcessors

NProcessors integer
Generic

Definition at line 20 of file avalon_bridge.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 9 of file avalon_bridge.vhd.

◆ reset

reset in std_logic
Port

Definition at line 30 of file avalon_bridge.vhd.

◆ s10_address

s10_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 240 of file avalon_bridge.vhd.

◆ s10_burstcount

s10_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 238 of file avalon_bridge.vhd.

◆ s10_byteenable

s10_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 243 of file avalon_bridge.vhd.

◆ s10_debugaccess

s10_debugaccess in std_logic
Port

Definition at line 244 of file avalon_bridge.vhd.

◆ s10_read

s10_read in std_logic
Port

Definition at line 242 of file avalon_bridge.vhd.

◆ s10_readdata

s10_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 236 of file avalon_bridge.vhd.

◆ s10_readdatavalid

s10_readdatavalid out std_logic
Port

Definition at line 237 of file avalon_bridge.vhd.

◆ s10_waitrequest

s10_waitrequest out std_logic
Port

Definition at line 235 of file avalon_bridge.vhd.

◆ s10_write

s10_write in std_logic
Port

Definition at line 241 of file avalon_bridge.vhd.

◆ s10_writedata

s10_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 239 of file avalon_bridge.vhd.

◆ s11_address

s11_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 262 of file avalon_bridge.vhd.

◆ s11_burstcount

s11_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 260 of file avalon_bridge.vhd.

◆ s11_byteenable

s11_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 265 of file avalon_bridge.vhd.

◆ s11_debugaccess

s11_debugaccess in std_logic
Port

Definition at line 266 of file avalon_bridge.vhd.

◆ s11_read

s11_read in std_logic
Port

Definition at line 264 of file avalon_bridge.vhd.

◆ s11_readdata

s11_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 258 of file avalon_bridge.vhd.

◆ s11_readdatavalid

s11_readdatavalid out std_logic
Port

Definition at line 259 of file avalon_bridge.vhd.

◆ s11_waitrequest

s11_waitrequest out std_logic
Port

Definition at line 257 of file avalon_bridge.vhd.

◆ s11_write

s11_write in std_logic
Port

Definition at line 263 of file avalon_bridge.vhd.

◆ s11_writedata

s11_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 261 of file avalon_bridge.vhd.

◆ s12_address

s12_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 284 of file avalon_bridge.vhd.

◆ s12_burstcount

s12_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 282 of file avalon_bridge.vhd.

◆ s12_byteenable

s12_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 287 of file avalon_bridge.vhd.

◆ s12_debugaccess

s12_debugaccess in std_logic
Port

Definition at line 288 of file avalon_bridge.vhd.

◆ s12_read

s12_read in std_logic
Port

Definition at line 286 of file avalon_bridge.vhd.

◆ s12_readdata

s12_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 280 of file avalon_bridge.vhd.

◆ s12_readdatavalid

s12_readdatavalid out std_logic
Port

Definition at line 281 of file avalon_bridge.vhd.

◆ s12_waitrequest

s12_waitrequest out std_logic
Port

Definition at line 279 of file avalon_bridge.vhd.

◆ s12_write

s12_write in std_logic
Port

Definition at line 285 of file avalon_bridge.vhd.

◆ s12_writedata

s12_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 283 of file avalon_bridge.vhd.

◆ s13_address

s13_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 306 of file avalon_bridge.vhd.

◆ s13_burstcount

s13_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 304 of file avalon_bridge.vhd.

◆ s13_byteenable

s13_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 309 of file avalon_bridge.vhd.

◆ s13_debugaccess

s13_debugaccess in std_logic
Port

Definition at line 310 of file avalon_bridge.vhd.

◆ s13_read

s13_read in std_logic
Port

Definition at line 308 of file avalon_bridge.vhd.

◆ s13_readdata

s13_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 302 of file avalon_bridge.vhd.

◆ s13_readdatavalid

s13_readdatavalid out std_logic
Port

Definition at line 303 of file avalon_bridge.vhd.

◆ s13_waitrequest

s13_waitrequest out std_logic
Port

Definition at line 301 of file avalon_bridge.vhd.

◆ s13_write

s13_write in std_logic
Port

Definition at line 307 of file avalon_bridge.vhd.

◆ s13_writedata

s13_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 305 of file avalon_bridge.vhd.

◆ s14_address

s14_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 328 of file avalon_bridge.vhd.

◆ s14_burstcount

s14_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 326 of file avalon_bridge.vhd.

◆ s14_byteenable

s14_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 331 of file avalon_bridge.vhd.

◆ s14_debugaccess

s14_debugaccess in std_logic
Port

Definition at line 332 of file avalon_bridge.vhd.

◆ s14_read

s14_read in std_logic
Port

Definition at line 330 of file avalon_bridge.vhd.

◆ s14_readdata

s14_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 324 of file avalon_bridge.vhd.

◆ s14_readdatavalid

s14_readdatavalid out std_logic
Port

Definition at line 325 of file avalon_bridge.vhd.

◆ s14_waitrequest

s14_waitrequest out std_logic
Port

Definition at line 323 of file avalon_bridge.vhd.

◆ s14_write

s14_write in std_logic
Port

Definition at line 329 of file avalon_bridge.vhd.

◆ s14_writedata

s14_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 327 of file avalon_bridge.vhd.

◆ s15_address

s15_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 350 of file avalon_bridge.vhd.

◆ s15_burstcount

s15_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 348 of file avalon_bridge.vhd.

◆ s15_byteenable

s15_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 353 of file avalon_bridge.vhd.

◆ s15_debugaccess

s15_debugaccess in std_logic
Port

Definition at line 354 of file avalon_bridge.vhd.

◆ s15_read

s15_read in std_logic
Port

Definition at line 352 of file avalon_bridge.vhd.

◆ s15_readdata

s15_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 346 of file avalon_bridge.vhd.

◆ s15_readdatavalid

s15_readdatavalid out std_logic
Port

Definition at line 347 of file avalon_bridge.vhd.

◆ s15_waitrequest

s15_waitrequest out std_logic
Port

Definition at line 345 of file avalon_bridge.vhd.

◆ s15_write

s15_write in std_logic
Port

Definition at line 351 of file avalon_bridge.vhd.

◆ s15_writedata

s15_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 349 of file avalon_bridge.vhd.

◆ s16_address

s16_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 372 of file avalon_bridge.vhd.

◆ s16_burstcount

s16_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 370 of file avalon_bridge.vhd.

◆ s16_byteenable

s16_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 375 of file avalon_bridge.vhd.

◆ s16_debugaccess

s16_debugaccess in std_logic
Port

Definition at line 376 of file avalon_bridge.vhd.

◆ s16_read

s16_read in std_logic
Port

Definition at line 374 of file avalon_bridge.vhd.

◆ s16_readdata

s16_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 368 of file avalon_bridge.vhd.

◆ s16_readdatavalid

s16_readdatavalid out std_logic
Port

Definition at line 369 of file avalon_bridge.vhd.

◆ s16_waitrequest

s16_waitrequest out std_logic
Port

Definition at line 367 of file avalon_bridge.vhd.

◆ s16_write

s16_write in std_logic
Port

Definition at line 373 of file avalon_bridge.vhd.

◆ s16_writedata

s16_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 371 of file avalon_bridge.vhd.

◆ s17_address

s17_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 394 of file avalon_bridge.vhd.

◆ s17_burstcount

s17_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 392 of file avalon_bridge.vhd.

◆ s17_byteenable

s17_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 397 of file avalon_bridge.vhd.

◆ s17_debugaccess

s17_debugaccess in std_logic
Port

Definition at line 398 of file avalon_bridge.vhd.

◆ s17_read

s17_read in std_logic
Port

Definition at line 396 of file avalon_bridge.vhd.

◆ s17_readdata

s17_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 390 of file avalon_bridge.vhd.

◆ s17_readdatavalid

s17_readdatavalid out std_logic
Port

Definition at line 391 of file avalon_bridge.vhd.

◆ s17_waitrequest

s17_waitrequest out std_logic
Port

Definition at line 389 of file avalon_bridge.vhd.

◆ s17_write

s17_write in std_logic
Port

Definition at line 395 of file avalon_bridge.vhd.

◆ s17_writedata

s17_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 393 of file avalon_bridge.vhd.

◆ s18_address

s18_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 416 of file avalon_bridge.vhd.

◆ s18_burstcount

s18_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 414 of file avalon_bridge.vhd.

◆ s18_byteenable

s18_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 419 of file avalon_bridge.vhd.

◆ s18_debugaccess

s18_debugaccess in std_logic
Port

Definition at line 420 of file avalon_bridge.vhd.

◆ s18_read

s18_read in std_logic
Port

Definition at line 418 of file avalon_bridge.vhd.

◆ s18_readdata

s18_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 412 of file avalon_bridge.vhd.

◆ s18_readdatavalid

s18_readdatavalid out std_logic
Port

Definition at line 413 of file avalon_bridge.vhd.

◆ s18_waitrequest

s18_waitrequest out std_logic
Port

Definition at line 411 of file avalon_bridge.vhd.

◆ s18_write

s18_write in std_logic
Port

Definition at line 417 of file avalon_bridge.vhd.

◆ s18_writedata

s18_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 415 of file avalon_bridge.vhd.

◆ s19_address

s19_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 438 of file avalon_bridge.vhd.

◆ s19_burstcount

s19_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 436 of file avalon_bridge.vhd.

◆ s19_byteenable

s19_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 441 of file avalon_bridge.vhd.

◆ s19_debugaccess

s19_debugaccess in std_logic
Port

Definition at line 442 of file avalon_bridge.vhd.

◆ s19_read

s19_read in std_logic
Port

Definition at line 440 of file avalon_bridge.vhd.

◆ s19_readdata

s19_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 434 of file avalon_bridge.vhd.

◆ s19_readdatavalid

s19_readdatavalid out std_logic
Port

Definition at line 435 of file avalon_bridge.vhd.

◆ s19_waitrequest

s19_waitrequest out std_logic
Port

Definition at line 433 of file avalon_bridge.vhd.

◆ s19_write

s19_write in std_logic
Port

Definition at line 439 of file avalon_bridge.vhd.

◆ s19_writedata

s19_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 437 of file avalon_bridge.vhd.

◆ s1_address

s1_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 42 of file avalon_bridge.vhd.

◆ s1_burstcount

s1_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 40 of file avalon_bridge.vhd.

◆ s1_byteenable

s1_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 45 of file avalon_bridge.vhd.

◆ s1_debugaccess

s1_debugaccess in std_logic
Port

Definition at line 46 of file avalon_bridge.vhd.

◆ s1_read

s1_read in std_logic
Port

Definition at line 44 of file avalon_bridge.vhd.

◆ s1_readdata

s1_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 38 of file avalon_bridge.vhd.

◆ s1_readdatavalid

s1_readdatavalid out std_logic
Port

Definition at line 39 of file avalon_bridge.vhd.

◆ s1_waitrequest

s1_waitrequest out std_logic
Port

Definition at line 37 of file avalon_bridge.vhd.

◆ s1_write

s1_write in std_logic
Port

Definition at line 43 of file avalon_bridge.vhd.

◆ s1_writedata

s1_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 41 of file avalon_bridge.vhd.

◆ s20_address

s20_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 460 of file avalon_bridge.vhd.

◆ s20_burstcount

s20_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 458 of file avalon_bridge.vhd.

◆ s20_byteenable

s20_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 463 of file avalon_bridge.vhd.

◆ s20_debugaccess

s20_debugaccess in std_logic
Port

Definition at line 464 of file avalon_bridge.vhd.

◆ s20_read

s20_read in std_logic
Port

Definition at line 462 of file avalon_bridge.vhd.

◆ s20_readdata

s20_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 456 of file avalon_bridge.vhd.

◆ s20_readdatavalid

s20_readdatavalid out std_logic
Port

Definition at line 457 of file avalon_bridge.vhd.

◆ s20_waitrequest

s20_waitrequest out std_logic
Port

Definition at line 455 of file avalon_bridge.vhd.

◆ s20_write

s20_write in std_logic
Port

Definition at line 461 of file avalon_bridge.vhd.

◆ s20_writedata

s20_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 459 of file avalon_bridge.vhd.

◆ s21_address

s21_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 482 of file avalon_bridge.vhd.

◆ s21_burstcount

s21_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 480 of file avalon_bridge.vhd.

◆ s21_byteenable

s21_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 485 of file avalon_bridge.vhd.

◆ s21_debugaccess

s21_debugaccess in std_logic
Port

Definition at line 486 of file avalon_bridge.vhd.

◆ s21_read

s21_read in std_logic
Port

Definition at line 484 of file avalon_bridge.vhd.

◆ s21_readdata

s21_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 478 of file avalon_bridge.vhd.

◆ s21_readdatavalid

s21_readdatavalid out std_logic
Port

Definition at line 479 of file avalon_bridge.vhd.

◆ s21_waitrequest

s21_waitrequest out std_logic
Port

Definition at line 477 of file avalon_bridge.vhd.

◆ s21_write

s21_write in std_logic
Port

Definition at line 483 of file avalon_bridge.vhd.

◆ s21_writedata

s21_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 481 of file avalon_bridge.vhd.

◆ s22_address

s22_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 504 of file avalon_bridge.vhd.

◆ s22_burstcount

s22_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 502 of file avalon_bridge.vhd.

◆ s22_byteenable

s22_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 507 of file avalon_bridge.vhd.

◆ s22_debugaccess

s22_debugaccess in std_logic
Port

Definition at line 508 of file avalon_bridge.vhd.

◆ s22_read

s22_read in std_logic
Port

Definition at line 506 of file avalon_bridge.vhd.

◆ s22_readdata

s22_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 500 of file avalon_bridge.vhd.

◆ s22_readdatavalid

s22_readdatavalid out std_logic
Port

Definition at line 501 of file avalon_bridge.vhd.

◆ s22_waitrequest

s22_waitrequest out std_logic
Port

Definition at line 499 of file avalon_bridge.vhd.

◆ s22_write

s22_write in std_logic
Port

Definition at line 505 of file avalon_bridge.vhd.

◆ s22_writedata

s22_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 503 of file avalon_bridge.vhd.

◆ s23_address

s23_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 526 of file avalon_bridge.vhd.

◆ s23_burstcount

s23_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 524 of file avalon_bridge.vhd.

◆ s23_byteenable

s23_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 529 of file avalon_bridge.vhd.

◆ s23_debugaccess

s23_debugaccess in std_logic
Port

Definition at line 530 of file avalon_bridge.vhd.

◆ s23_read

s23_read in std_logic
Port

Definition at line 528 of file avalon_bridge.vhd.

◆ s23_readdata

s23_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 522 of file avalon_bridge.vhd.

◆ s23_readdatavalid

s23_readdatavalid out std_logic
Port

Definition at line 523 of file avalon_bridge.vhd.

◆ s23_waitrequest

s23_waitrequest out std_logic
Port

Definition at line 521 of file avalon_bridge.vhd.

◆ s23_write

s23_write in std_logic
Port

Definition at line 527 of file avalon_bridge.vhd.

◆ s23_writedata

s23_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 525 of file avalon_bridge.vhd.

◆ s24_address

s24_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 548 of file avalon_bridge.vhd.

◆ s24_burstcount

s24_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 546 of file avalon_bridge.vhd.

◆ s24_byteenable

s24_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 551 of file avalon_bridge.vhd.

◆ s24_debugaccess

s24_debugaccess in std_logic
Port

Definition at line 552 of file avalon_bridge.vhd.

◆ s24_read

s24_read in std_logic
Port

Definition at line 550 of file avalon_bridge.vhd.

◆ s24_readdata

s24_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 544 of file avalon_bridge.vhd.

◆ s24_readdatavalid

s24_readdatavalid out std_logic
Port

Definition at line 545 of file avalon_bridge.vhd.

◆ s24_waitrequest

s24_waitrequest out std_logic
Port

Definition at line 543 of file avalon_bridge.vhd.

◆ s24_write

s24_write in std_logic
Port

Definition at line 549 of file avalon_bridge.vhd.

◆ s24_writedata

s24_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 547 of file avalon_bridge.vhd.

◆ s25_address

s25_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 570 of file avalon_bridge.vhd.

◆ s25_burstcount

s25_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 568 of file avalon_bridge.vhd.

◆ s25_byteenable

s25_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 573 of file avalon_bridge.vhd.

◆ s25_debugaccess

s25_debugaccess in std_logic
Port

Definition at line 574 of file avalon_bridge.vhd.

◆ s25_read

s25_read in std_logic
Port

Definition at line 572 of file avalon_bridge.vhd.

◆ s25_readdata

s25_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 566 of file avalon_bridge.vhd.

◆ s25_readdatavalid

s25_readdatavalid out std_logic
Port

Definition at line 567 of file avalon_bridge.vhd.

◆ s25_waitrequest

s25_waitrequest out std_logic
Port

Definition at line 565 of file avalon_bridge.vhd.

◆ s25_write

s25_write in std_logic
Port

Definition at line 571 of file avalon_bridge.vhd.

◆ s25_writedata

s25_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 569 of file avalon_bridge.vhd.

◆ s26_address

s26_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 592 of file avalon_bridge.vhd.

◆ s26_burstcount

s26_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 590 of file avalon_bridge.vhd.

◆ s26_byteenable

s26_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 595 of file avalon_bridge.vhd.

◆ s26_debugaccess

s26_debugaccess in std_logic
Port

Definition at line 596 of file avalon_bridge.vhd.

◆ s26_read

s26_read in std_logic
Port

Definition at line 594 of file avalon_bridge.vhd.

◆ s26_readdata

s26_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 588 of file avalon_bridge.vhd.

◆ s26_readdatavalid

s26_readdatavalid out std_logic
Port

Definition at line 589 of file avalon_bridge.vhd.

◆ s26_waitrequest

s26_waitrequest out std_logic
Port

Definition at line 587 of file avalon_bridge.vhd.

◆ s26_write

s26_write in std_logic
Port

Definition at line 593 of file avalon_bridge.vhd.

◆ s26_writedata

s26_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 591 of file avalon_bridge.vhd.

◆ s27_address

s27_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 614 of file avalon_bridge.vhd.

◆ s27_burstcount

s27_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 612 of file avalon_bridge.vhd.

◆ s27_byteenable

s27_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 617 of file avalon_bridge.vhd.

◆ s27_debugaccess

s27_debugaccess in std_logic
Port

Definition at line 618 of file avalon_bridge.vhd.

◆ s27_read

s27_read in std_logic
Port

Definition at line 616 of file avalon_bridge.vhd.

◆ s27_readdata

s27_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 610 of file avalon_bridge.vhd.

◆ s27_readdatavalid

s27_readdatavalid out std_logic
Port

Definition at line 611 of file avalon_bridge.vhd.

◆ s27_waitrequest

s27_waitrequest out std_logic
Port

Definition at line 609 of file avalon_bridge.vhd.

◆ s27_write

s27_write in std_logic
Port

Definition at line 615 of file avalon_bridge.vhd.

◆ s27_writedata

s27_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 613 of file avalon_bridge.vhd.

◆ s28_address

s28_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 636 of file avalon_bridge.vhd.

◆ s28_burstcount

s28_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 634 of file avalon_bridge.vhd.

◆ s28_byteenable

s28_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 639 of file avalon_bridge.vhd.

◆ s28_debugaccess

s28_debugaccess in std_logic
Port

Definition at line 640 of file avalon_bridge.vhd.

◆ s28_read

s28_read in std_logic
Port

Definition at line 638 of file avalon_bridge.vhd.

◆ s28_readdata

s28_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 632 of file avalon_bridge.vhd.

◆ s28_readdatavalid

s28_readdatavalid out std_logic
Port

Definition at line 633 of file avalon_bridge.vhd.

◆ s28_waitrequest

s28_waitrequest out std_logic
Port

Definition at line 631 of file avalon_bridge.vhd.

◆ s28_write

s28_write in std_logic
Port

Definition at line 637 of file avalon_bridge.vhd.

◆ s28_writedata

s28_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 635 of file avalon_bridge.vhd.

◆ s29_address

s29_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 658 of file avalon_bridge.vhd.

◆ s29_burstcount

s29_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 656 of file avalon_bridge.vhd.

◆ s29_byteenable

s29_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 661 of file avalon_bridge.vhd.

◆ s29_debugaccess

s29_debugaccess in std_logic
Port

Definition at line 662 of file avalon_bridge.vhd.

◆ s29_read

s29_read in std_logic
Port

Definition at line 660 of file avalon_bridge.vhd.

◆ s29_readdata

s29_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 654 of file avalon_bridge.vhd.

◆ s29_readdatavalid

s29_readdatavalid out std_logic
Port

Definition at line 655 of file avalon_bridge.vhd.

◆ s29_waitrequest

s29_waitrequest out std_logic
Port

Definition at line 653 of file avalon_bridge.vhd.

◆ s29_write

s29_write in std_logic
Port

Definition at line 659 of file avalon_bridge.vhd.

◆ s29_writedata

s29_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 657 of file avalon_bridge.vhd.

◆ s2_address

s2_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 64 of file avalon_bridge.vhd.

◆ s2_burstcount

s2_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 62 of file avalon_bridge.vhd.

◆ s2_byteenable

s2_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 67 of file avalon_bridge.vhd.

◆ s2_debugaccess

s2_debugaccess in std_logic
Port

Definition at line 68 of file avalon_bridge.vhd.

◆ s2_read

s2_read in std_logic
Port

Definition at line 66 of file avalon_bridge.vhd.

◆ s2_readdata

s2_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 60 of file avalon_bridge.vhd.

◆ s2_readdatavalid

s2_readdatavalid out std_logic
Port

Definition at line 61 of file avalon_bridge.vhd.

◆ s2_waitrequest

s2_waitrequest out std_logic
Port

Definition at line 59 of file avalon_bridge.vhd.

◆ s2_write

s2_write in std_logic
Port

Definition at line 65 of file avalon_bridge.vhd.

◆ s2_writedata

s2_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 63 of file avalon_bridge.vhd.

◆ s30_address

s30_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 680 of file avalon_bridge.vhd.

◆ s30_burstcount

s30_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 678 of file avalon_bridge.vhd.

◆ s30_byteenable

s30_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 683 of file avalon_bridge.vhd.

◆ s30_debugaccess

s30_debugaccess in std_logic
Port

Definition at line 684 of file avalon_bridge.vhd.

◆ s30_read

s30_read in std_logic
Port

Definition at line 682 of file avalon_bridge.vhd.

◆ s30_readdata

s30_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 676 of file avalon_bridge.vhd.

◆ s30_readdatavalid

s30_readdatavalid out std_logic
Port

Definition at line 677 of file avalon_bridge.vhd.

◆ s30_waitrequest

s30_waitrequest out std_logic
Port

Definition at line 675 of file avalon_bridge.vhd.

◆ s30_write

s30_write in std_logic
Port

Definition at line 681 of file avalon_bridge.vhd.

◆ s30_writedata

s30_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 679 of file avalon_bridge.vhd.

◆ s31_address

s31_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 702 of file avalon_bridge.vhd.

◆ s31_burstcount

s31_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 700 of file avalon_bridge.vhd.

◆ s31_byteenable

s31_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 705 of file avalon_bridge.vhd.

◆ s31_debugaccess

s31_debugaccess in std_logic
Port

Definition at line 706 of file avalon_bridge.vhd.

◆ s31_read

s31_read in std_logic
Port

Definition at line 704 of file avalon_bridge.vhd.

◆ s31_readdata

s31_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 698 of file avalon_bridge.vhd.

◆ s31_readdatavalid

s31_readdatavalid out std_logic
Port

Definition at line 699 of file avalon_bridge.vhd.

◆ s31_waitrequest

s31_waitrequest out std_logic
Port

Definition at line 697 of file avalon_bridge.vhd.

◆ s31_write

s31_write in std_logic
Port

Definition at line 703 of file avalon_bridge.vhd.

◆ s31_writedata

s31_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 701 of file avalon_bridge.vhd.

◆ s32_address

s32_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 724 of file avalon_bridge.vhd.

◆ s32_burstcount

s32_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 722 of file avalon_bridge.vhd.

◆ s32_byteenable

s32_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 727 of file avalon_bridge.vhd.

◆ s32_debugaccess

s32_debugaccess in std_logic
Port

Definition at line 728 of file avalon_bridge.vhd.

◆ s32_read

s32_read in std_logic
Port

Definition at line 726 of file avalon_bridge.vhd.

◆ s32_readdata

s32_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 720 of file avalon_bridge.vhd.

◆ s32_readdatavalid

s32_readdatavalid out std_logic
Port

Definition at line 721 of file avalon_bridge.vhd.

◆ s32_waitrequest

s32_waitrequest out std_logic
Port

Definition at line 719 of file avalon_bridge.vhd.

◆ s32_write

s32_write in std_logic
Port

Definition at line 725 of file avalon_bridge.vhd.

◆ s32_writedata

s32_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 723 of file avalon_bridge.vhd.

◆ s3_address

s3_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 86 of file avalon_bridge.vhd.

◆ s3_burstcount

s3_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 84 of file avalon_bridge.vhd.

◆ s3_byteenable

s3_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 89 of file avalon_bridge.vhd.

◆ s3_debugaccess

s3_debugaccess in std_logic
Port

Definition at line 90 of file avalon_bridge.vhd.

◆ s3_read

s3_read in std_logic
Port

Definition at line 88 of file avalon_bridge.vhd.

◆ s3_readdata

s3_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 82 of file avalon_bridge.vhd.

◆ s3_readdatavalid

s3_readdatavalid out std_logic
Port

Definition at line 83 of file avalon_bridge.vhd.

◆ s3_waitrequest

s3_waitrequest out std_logic
Port

Definition at line 81 of file avalon_bridge.vhd.

◆ s3_write

s3_write in std_logic
Port

Definition at line 87 of file avalon_bridge.vhd.

◆ s3_writedata

s3_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 85 of file avalon_bridge.vhd.

◆ s4_address

s4_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 108 of file avalon_bridge.vhd.

◆ s4_burstcount

s4_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 106 of file avalon_bridge.vhd.

◆ s4_byteenable

s4_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 111 of file avalon_bridge.vhd.

◆ s4_debugaccess

s4_debugaccess in std_logic
Port

Definition at line 112 of file avalon_bridge.vhd.

◆ s4_read

s4_read in std_logic
Port

Definition at line 110 of file avalon_bridge.vhd.

◆ s4_readdata

s4_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 104 of file avalon_bridge.vhd.

◆ s4_readdatavalid

s4_readdatavalid out std_logic
Port

Definition at line 105 of file avalon_bridge.vhd.

◆ s4_waitrequest

s4_waitrequest out std_logic
Port

Definition at line 103 of file avalon_bridge.vhd.

◆ s4_write

s4_write in std_logic
Port

Definition at line 109 of file avalon_bridge.vhd.

◆ s4_writedata

s4_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 107 of file avalon_bridge.vhd.

◆ s5_address

s5_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 130 of file avalon_bridge.vhd.

◆ s5_burstcount

s5_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 128 of file avalon_bridge.vhd.

◆ s5_byteenable

s5_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 133 of file avalon_bridge.vhd.

◆ s5_debugaccess

s5_debugaccess in std_logic
Port

Definition at line 134 of file avalon_bridge.vhd.

◆ s5_read

s5_read in std_logic
Port

Definition at line 132 of file avalon_bridge.vhd.

◆ s5_readdata

s5_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 126 of file avalon_bridge.vhd.

◆ s5_readdatavalid

s5_readdatavalid out std_logic
Port

Definition at line 127 of file avalon_bridge.vhd.

◆ s5_waitrequest

s5_waitrequest out std_logic
Port

Definition at line 125 of file avalon_bridge.vhd.

◆ s5_write

s5_write in std_logic
Port

Definition at line 131 of file avalon_bridge.vhd.

◆ s5_writedata

s5_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 129 of file avalon_bridge.vhd.

◆ s6_address

s6_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 152 of file avalon_bridge.vhd.

◆ s6_burstcount

s6_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 150 of file avalon_bridge.vhd.

◆ s6_byteenable

s6_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 155 of file avalon_bridge.vhd.

◆ s6_debugaccess

s6_debugaccess in std_logic
Port

Definition at line 156 of file avalon_bridge.vhd.

◆ s6_read

s6_read in std_logic
Port

Definition at line 154 of file avalon_bridge.vhd.

◆ s6_readdata

s6_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 148 of file avalon_bridge.vhd.

◆ s6_readdatavalid

s6_readdatavalid out std_logic
Port

Definition at line 149 of file avalon_bridge.vhd.

◆ s6_waitrequest

s6_waitrequest out std_logic
Port

Definition at line 147 of file avalon_bridge.vhd.

◆ s6_write

s6_write in std_logic
Port

Definition at line 153 of file avalon_bridge.vhd.

◆ s6_writedata

s6_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 151 of file avalon_bridge.vhd.

◆ s7_address

s7_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 174 of file avalon_bridge.vhd.

◆ s7_burstcount

s7_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 172 of file avalon_bridge.vhd.

◆ s7_byteenable

s7_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 177 of file avalon_bridge.vhd.

◆ s7_debugaccess

s7_debugaccess in std_logic
Port

Definition at line 178 of file avalon_bridge.vhd.

◆ s7_read

s7_read in std_logic
Port

Definition at line 176 of file avalon_bridge.vhd.

◆ s7_readdata

s7_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 170 of file avalon_bridge.vhd.

◆ s7_readdatavalid

s7_readdatavalid out std_logic
Port

Definition at line 171 of file avalon_bridge.vhd.

◆ s7_waitrequest

s7_waitrequest out std_logic
Port

Definition at line 169 of file avalon_bridge.vhd.

◆ s7_write

s7_write in std_logic
Port

Definition at line 175 of file avalon_bridge.vhd.

◆ s7_writedata

s7_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 173 of file avalon_bridge.vhd.

◆ s8_address

s8_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 196 of file avalon_bridge.vhd.

◆ s8_burstcount

s8_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 194 of file avalon_bridge.vhd.

◆ s8_byteenable

s8_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 199 of file avalon_bridge.vhd.

◆ s8_debugaccess

s8_debugaccess in std_logic
Port

Definition at line 200 of file avalon_bridge.vhd.

◆ s8_read

s8_read in std_logic
Port

Definition at line 198 of file avalon_bridge.vhd.

◆ s8_readdata

s8_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 192 of file avalon_bridge.vhd.

◆ s8_readdatavalid

s8_readdatavalid out std_logic
Port

Definition at line 193 of file avalon_bridge.vhd.

◆ s8_waitrequest

s8_waitrequest out std_logic
Port

Definition at line 191 of file avalon_bridge.vhd.

◆ s8_write

s8_write in std_logic
Port

Definition at line 197 of file avalon_bridge.vhd.

◆ s8_writedata

s8_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 195 of file avalon_bridge.vhd.

◆ s9_address

s9_address in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 )
Port

Definition at line 218 of file avalon_bridge.vhd.

◆ s9_burstcount

s9_burstcount in std_logic_vector ( BURSTCOUNT_WIDTH - 1 downto 0 )
Port

Definition at line 216 of file avalon_bridge.vhd.

◆ s9_byteenable

s9_byteenable in std_logic_vector ( BYTEEN_WIDTH - 1 downto 0 )
Port

Definition at line 221 of file avalon_bridge.vhd.

◆ s9_debugaccess

s9_debugaccess in std_logic
Port

Definition at line 222 of file avalon_bridge.vhd.

◆ s9_read

s9_read in std_logic
Port

Definition at line 220 of file avalon_bridge.vhd.

◆ s9_readdata

s9_readdata out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 214 of file avalon_bridge.vhd.

◆ s9_readdatavalid

s9_readdatavalid out std_logic
Port

Definition at line 215 of file avalon_bridge.vhd.

◆ s9_waitrequest

s9_waitrequest out std_logic
Port

Definition at line 213 of file avalon_bridge.vhd.

◆ s9_write

s9_write in std_logic
Port

Definition at line 219 of file avalon_bridge.vhd.

◆ s9_writedata

s9_writedata in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
Port

Definition at line 217 of file avalon_bridge.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 7 of file avalon_bridge.vhd.

◆ std_logic_unsigned

std_logic_unsigned
use clause

Definition at line 8 of file avalon_bridge.vhd.

The documentation for this class was generated from the following file:
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