STD_FIFO Entity Reference

Inheritance diagram for STD_FIFO:

Entities
Behavioral	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Generics
DATA_WIDTH	positive := 8
FIFO_DEPTH	positive := 256

Ports
CLK	in	STD_LOGIC
RST	in	STD_LOGIC
WriteEn	in	STD_LOGIC
DataIn	in	STD_LOGIC_VECTOR ( DATA_WIDTH - 1 downto 0 )
ReadEn	in	STD_LOGIC
DataOut	out	STD_LOGIC_VECTOR ( DATA_WIDTH - 1 downto 0 )
Empty	out	STD_LOGIC
Almost_Full	out	STD_LOGIC
Full	out	STD_LOGIC

Detailed Description

Definition at line 5 of file STD_FIFO.vhd.

Field Documentation

Almost_Full

Almost_Full out STD_LOGIC

Port

Definition at line 18 of file STD_FIFO.vhd.

CLK

CLK in STD_LOGIC

Port

Definition at line 11 of file STD_FIFO.vhd.

DATA_WIDTH

DATA_WIDTH positive := 8

Generic

Definition at line 7 of file STD_FIFO.vhd.

DataIn

DataIn in STD_LOGIC_VECTOR ( DATA_WIDTH - 1 downto 0 )

Port

Definition at line 14 of file STD_FIFO.vhd.

DataOut

DataOut out STD_LOGIC_VECTOR ( DATA_WIDTH - 1 downto 0 )

Port

Definition at line 16 of file STD_FIFO.vhd.

Empty

Empty out STD_LOGIC

Port

Definition at line 17 of file STD_FIFO.vhd.

FIFO_DEPTH

FIFO_DEPTH positive := 256

Generic

Definition at line 9 of file STD_FIFO.vhd.

Full

Full out STD_LOGIC

Port

Definition at line 20 of file STD_FIFO.vhd.

IEEE

IEEE

Library

Definition at line 1 of file STD_FIFO.vhd.

NUMERIC_STD

NUMERIC_STD

use clause

Definition at line 3 of file STD_FIFO.vhd.

ReadEn

ReadEn in STD_LOGIC

Port

Definition at line 15 of file STD_FIFO.vhd.

RST

RST in STD_LOGIC

Port

Definition at line 12 of file STD_FIFO.vhd.

STD_LOGIC_1164

STD_LOGIC_1164

use clause

Definition at line 2 of file STD_FIFO.vhd.

WriteEn

WriteEn in STD_LOGIC

Port

Definition at line 13 of file STD_FIFO.vhd.

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The documentation for this class was generated from the following file:

• misc/gemrtos_ips/AvalonMonitor/STD_FIFO.vhd