Step 6: Design the Intel’s Platform Designer system
As with uniprocessor systems based on Nios II or Nios V processors, the remaining components in the system must be added and interconnected. If the “Independent External Processor Buses” option is enabled, each processor bus must be connected to the appropriate devices. Memory devices should be connected before selecting the Reset and Exception Vector Memory, as valid options are derived from the memory devices attached to the bus of the processor with an ID equal to 1. Figure 10 provides an example of how the 10 processor buses of the GeMRTOS Multiprocessor-based system are connected to a 34404-byte on-chip memory in a DE2-115 board to store the entire application. Additionally, the GeMRTOS Multiprocessor buses are connected to the PLL device, and they can be connected to any other component in the system.
Similar to Nios II or Nios V processors, interrupt signals must be connected to the gemrtos_dirq_input port of the GeMRTOS Multiprocessor component. The GeMRTOS Multiprocessor component significantly simplifies the design of multiprocessor systems in much the same way as uniprocessor designs. It helps manage complexities such as exclusion components, boot synchronization, interrupt management, system time management, and processor identification.