GeMRTOS: Multiprocessor RTOS – Reference Design

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Step 2: Generate the Altera’s Platform Designer project

This step generates the Altera’s Platform Designer system, producing files for synthesis and the .sopcinfo file. This can be achieved by executing the following command:

  • for Nios II:
qsys-generate.exe <Platform_Designer_project_name>.qsys --synthesis=VERILOG
  • for Nios V:
%QSYS_ROOTDIR%/qsys-generate <Platform_Designer_project_name>.qsys --synthesis=VERILOG

Note: This command performs the same action as clicking the “Generate HDL” button in Altera’s Platform Designer. The gemrtos_build script also handles this step automatically, but the project name can be overridden using the -qsys option.

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