Step 7: Build the Intel’s Platform Designer system and compile the Quartus Prime project
Once the design is complete, the system should be generated in Intel’s Platform Designer, and the GeMRTOS Multiprocessor component should be instantiated in the Quartus Prime project. This step is necessary for compiling the final hardware configuration for the FPGA board. The component in the Quartus Prime project may also need modifications to include conduit ports added by the GeMRTOS Multiprocessor component. These modifications are straightforward if the new signals are incorporated in a manner similar to the existing ones in the project.
Upon completion of all steps, a .sof or .pof file will be generated to program the FPGA device. After generating the system in Intel’s Platform Designer, a .sopcinfo file is created, containing all the necessary information to generate the BSP project (Board Support Package), which serves as the software layer supporting the user application.
Figure 11 illustrates the layout of the hardware creation flow, following the design methodology proposed by Intel/Altera for implementing embedded SOPC systems on FPGA devices. This flow outlines the step-by-step process involved in configuring and designing hardware components, using tools such as Quartus Prime and Intel’s Platform Designer to integrate various elements, including the GeMRTOS Multiprocessor system, into the FPGA architecture.
The software creation flow is detailed in the next section and follows a process similar to that for uniprocessor systems based on Nios II or Nios V processors.