GeMRTOS
avalon_monitor.vhd
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1 -- $Id: //avalon_monitor.vhd#1 $
2 -- $Revision: #1 $
3 -- $Date: 2017/03/06 $
4 -- $Author: Ricardo Cayssials $
5 -- --------------------------------------
6 library ieee;
7 use ieee.std_logic_1164.all;
8 use ieee.std_logic_unsigned.all;
9 use ieee.numeric_std.all;
10 
11 LIBRARY altera_mf;
12 USE altera_mf.all;
13 
14 
15 
16 entity avalon_monitor is
17 
18  generic
19  (
20  NProcessors : integer;
21  DATA_WIDTH : integer := 32;
22  SYMBOL_WIDTH : integer := 8;
23  ADDRESS_WIDTH : integer := 32;
24  BURSTCOUNT_WIDTH : integer := 1;
25  BYTEEN_WIDTH : integer := 4;
26  AVALON_DATA_FIFO_DEPTH : integer := 8; -- AVALON_DATA_FIFO_WIDTHU : integer := 3;
27  DEVICE_FAMILY : string
28  );
29 
30  port (
31  clk : in std_logic;
32  reset : in std_logic;
33 
34  -- Ouput indicating a processor is in waiting
35  frozen_avalon_monitor : out std_logic;
36 
37  -- Avalon Slave port to Access monitor Registers
38  slave_AvalonMonitor_chipselect : in std_logic;
39  slave_AvalonMonitor_address : in std_logic_vector(5 downto 0);
40  slave_AvalonMonitor_read : in std_logic;
41  slave_AvalonMonitor_write : in std_logic;
42  slave_AvalonMonitor_readdata : out std_logic_vector(31 downto 0);
43  slave_AvalonMonitor_writedata : in std_logic_vector(31 downto 0);
44 
45  -- #####################################################################
46  -- Ports for avalon sniffer
47  -- #####################################################################
48  -- Processor 1
49  s1_waitrequest : out std_logic;
50  s1_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
51  s1_readdatavalid : out std_logic;
52  s1_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
53  s1_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
54  s1_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
55  s1_write : in std_logic;
56  s1_read : in std_logic;
57  s1_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
58  s1_debugaccess : in std_logic;
59  m1_waitrequest : in std_logic;
60  m1_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
61  m1_readdatavalid : in std_logic;
62  m1_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
63  m1_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
64  m1_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
65  m1_write : out std_logic;
66  m1_read : out std_logic;
67  m1_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
68  m1_debugaccess : out std_logic;
69  -- #####################################################################
70  -- Processor 2
71  s2_waitrequest : out std_logic;
72  s2_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
73  s2_readdatavalid : out std_logic;
74  s2_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
75  s2_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
76  s2_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
77  s2_write : in std_logic;
78  s2_read : in std_logic;
79  s2_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
80  s2_debugaccess : in std_logic;
81  m2_waitrequest : in std_logic;
82  m2_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
83  m2_readdatavalid : in std_logic;
84  m2_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
85  m2_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
86  m2_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
87  m2_write : out std_logic;
88  m2_read : out std_logic;
89  m2_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
90  m2_debugaccess : out std_logic;
91  -- #####################################################################
92  -- Processor 3
93  s3_waitrequest : out std_logic;
94  s3_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
95  s3_readdatavalid : out std_logic;
96  s3_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
97  s3_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
98  s3_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
99  s3_write : in std_logic;
100  s3_read : in std_logic;
101  s3_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
102  s3_debugaccess : in std_logic;
103  m3_waitrequest : in std_logic;
104  m3_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
105  m3_readdatavalid : in std_logic;
106  m3_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
107  m3_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
108  m3_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
109  m3_write : out std_logic;
110  m3_read : out std_logic;
111  m3_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
112  m3_debugaccess : out std_logic;
113  -- #####################################################################
114  -- Processor 4
115  s4_waitrequest : out std_logic;
116  s4_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
117  s4_readdatavalid : out std_logic;
118  s4_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
119  s4_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
120  s4_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
121  s4_write : in std_logic;
122  s4_read : in std_logic;
123  s4_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
124  s4_debugaccess : in std_logic;
125  m4_waitrequest : in std_logic;
126  m4_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
127  m4_readdatavalid : in std_logic;
128  m4_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
129  m4_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
130  m4_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
131  m4_write : out std_logic;
132  m4_read : out std_logic;
133  m4_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
134  m4_debugaccess : out std_logic;
135  -- #####################################################################
136  -- Processor 5
137  s5_waitrequest : out std_logic;
138  s5_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
139  s5_readdatavalid : out std_logic;
140  s5_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
141  s5_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
142  s5_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
143  s5_write : in std_logic;
144  s5_read : in std_logic;
145  s5_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
146  s5_debugaccess : in std_logic;
147  m5_waitrequest : in std_logic;
148  m5_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
149  m5_readdatavalid : in std_logic;
150  m5_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
151  m5_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
152  m5_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
153  m5_write : out std_logic;
154  m5_read : out std_logic;
155  m5_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
156  m5_debugaccess : out std_logic;
157  -- #####################################################################
158  -- Processor 6
159  s6_waitrequest : out std_logic;
160  s6_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
161  s6_readdatavalid : out std_logic;
162  s6_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
163  s6_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
164  s6_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
165  s6_write : in std_logic;
166  s6_read : in std_logic;
167  s6_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
168  s6_debugaccess : in std_logic;
169  m6_waitrequest : in std_logic;
170  m6_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
171  m6_readdatavalid : in std_logic;
172  m6_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
173  m6_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
174  m6_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
175  m6_write : out std_logic;
176  m6_read : out std_logic;
177  m6_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
178  m6_debugaccess : out std_logic;
179  -- #####################################################################
180  -- Processor 7
181  s7_waitrequest : out std_logic;
182  s7_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
183  s7_readdatavalid : out std_logic;
184  s7_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
185  s7_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
186  s7_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
187  s7_write : in std_logic;
188  s7_read : in std_logic;
189  s7_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
190  s7_debugaccess : in std_logic;
191  m7_waitrequest : in std_logic;
192  m7_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
193  m7_readdatavalid : in std_logic;
194  m7_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
195  m7_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
196  m7_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
197  m7_write : out std_logic;
198  m7_read : out std_logic;
199  m7_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
200  m7_debugaccess : out std_logic;
201  -- #####################################################################
202  -- Processor 8
203  s8_waitrequest : out std_logic;
204  s8_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
205  s8_readdatavalid : out std_logic;
206  s8_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
207  s8_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
208  s8_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
209  s8_write : in std_logic;
210  s8_read : in std_logic;
211  s8_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
212  s8_debugaccess : in std_logic;
213  m8_waitrequest : in std_logic;
214  m8_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
215  m8_readdatavalid : in std_logic;
216  m8_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
217  m8_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
218  m8_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
219  m8_write : out std_logic;
220  m8_read : out std_logic;
221  m8_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
222  m8_debugaccess : out std_logic;
223  -- #####################################################################
224  -- Processor 9
225  s9_waitrequest : out std_logic;
226  s9_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
227  s9_readdatavalid : out std_logic;
228  s9_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
229  s9_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
230  s9_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
231  s9_write : in std_logic;
232  s9_read : in std_logic;
233  s9_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
234  s9_debugaccess : in std_logic;
235  m9_waitrequest : in std_logic;
236  m9_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
237  m9_readdatavalid : in std_logic;
238  m9_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
239  m9_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
240  m9_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
241  m9_write : out std_logic;
242  m9_read : out std_logic;
243  m9_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
244  m9_debugaccess : out std_logic;
245  -- #####################################################################
246  -- Processor 10
247  s10_waitrequest : out std_logic;
248  s10_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
249  s10_readdatavalid : out std_logic;
250  s10_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
251  s10_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
252  s10_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
253  s10_write : in std_logic;
254  s10_read : in std_logic;
255  s10_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
256  s10_debugaccess : in std_logic;
257  m10_waitrequest : in std_logic;
258  m10_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
259  m10_readdatavalid : in std_logic;
260  m10_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
261  m10_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
262  m10_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
263  m10_write : out std_logic;
264  m10_read : out std_logic;
265  m10_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
266  m10_debugaccess : out std_logic;
267  -- #####################################################################
268  -- Processor 11
269  s11_waitrequest : out std_logic;
270  s11_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
271  s11_readdatavalid : out std_logic;
272  s11_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
273  s11_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
274  s11_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
275  s11_write : in std_logic;
276  s11_read : in std_logic;
277  s11_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
278  s11_debugaccess : in std_logic;
279  m11_waitrequest : in std_logic;
280  m11_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
281  m11_readdatavalid : in std_logic;
282  m11_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
283  m11_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
284  m11_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
285  m11_write : out std_logic;
286  m11_read : out std_logic;
287  m11_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
288  m11_debugaccess : out std_logic;
289  -- #####################################################################
290  -- Processor 12
291  s12_waitrequest : out std_logic;
292  s12_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
293  s12_readdatavalid : out std_logic;
294  s12_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
295  s12_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
296  s12_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
297  s12_write : in std_logic;
298  s12_read : in std_logic;
299  s12_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
300  s12_debugaccess : in std_logic;
301  m12_waitrequest : in std_logic;
302  m12_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
303  m12_readdatavalid : in std_logic;
304  m12_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
305  m12_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
306  m12_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
307  m12_write : out std_logic;
308  m12_read : out std_logic;
309  m12_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
310  m12_debugaccess : out std_logic;
311  -- #####################################################################
312  -- Processor 13
313  s13_waitrequest : out std_logic;
314  s13_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
315  s13_readdatavalid : out std_logic;
316  s13_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
317  s13_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
318  s13_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
319  s13_write : in std_logic;
320  s13_read : in std_logic;
321  s13_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
322  s13_debugaccess : in std_logic;
323  m13_waitrequest : in std_logic;
324  m13_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
325  m13_readdatavalid : in std_logic;
326  m13_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
327  m13_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
328  m13_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
329  m13_write : out std_logic;
330  m13_read : out std_logic;
331  m13_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
332  m13_debugaccess : out std_logic;
333  -- #####################################################################
334  -- Processor 13
335  s14_waitrequest : out std_logic;
336  s14_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
337  s14_readdatavalid : out std_logic;
338  s14_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
339  s14_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
340  s14_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
341  s14_write : in std_logic;
342  s14_read : in std_logic;
343  s14_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
344  s14_debugaccess : in std_logic;
345  m14_waitrequest : in std_logic;
346  m14_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
347  m14_readdatavalid : in std_logic;
348  m14_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
349  m14_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
350  m14_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
351  m14_write : out std_logic;
352  m14_read : out std_logic;
353  m14_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
354  m14_debugaccess : out std_logic;
355  -- #####################################################################
356  -- Processor 14
357  s15_waitrequest : out std_logic;
358  s15_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
359  s15_readdatavalid : out std_logic;
360  s15_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
361  s15_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
362  s15_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
363  s15_write : in std_logic;
364  s15_read : in std_logic;
365  s15_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
366  s15_debugaccess : in std_logic;
367  m15_waitrequest : in std_logic;
368  m15_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
369  m15_readdatavalid : in std_logic;
370  m15_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
371  m15_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
372  m15_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
373  m15_write : out std_logic;
374  m15_read : out std_logic;
375  m15_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
376  m15_debugaccess : out std_logic;
377  -- #####################################################################
378  -- Processor 16
379  s16_waitrequest : out std_logic;
380  s16_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
381  s16_readdatavalid : out std_logic;
382  s16_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
383  s16_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
384  s16_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
385  s16_write : in std_logic;
386  s16_read : in std_logic;
387  s16_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
388  s16_debugaccess : in std_logic;
389  m16_waitrequest : in std_logic;
390  m16_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
391  m16_readdatavalid : in std_logic;
392  m16_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
393  m16_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
394  m16_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
395  m16_write : out std_logic;
396  m16_read : out std_logic;
397  m16_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
398  m16_debugaccess : out std_logic;
399  -- #####################################################################
400  -- Processor 17
401  s17_waitrequest : out std_logic;
402  s17_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
403  s17_readdatavalid : out std_logic;
404  s17_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
405  s17_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
406  s17_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
407  s17_write : in std_logic;
408  s17_read : in std_logic;
409  s17_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
410  s17_debugaccess : in std_logic;
411  m17_waitrequest : in std_logic;
412  m17_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
413  m17_readdatavalid : in std_logic;
414  m17_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
415  m17_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
416  m17_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
417  m17_write : out std_logic;
418  m17_read : out std_logic;
419  m17_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
420  m17_debugaccess : out std_logic;
421  -- #####################################################################
422  -- Processor 18
423  s18_waitrequest : out std_logic;
424  s18_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
425  s18_readdatavalid : out std_logic;
426  s18_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
427  s18_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
428  s18_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
429  s18_write : in std_logic;
430  s18_read : in std_logic;
431  s18_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
432  s18_debugaccess : in std_logic;
433  m18_waitrequest : in std_logic;
434  m18_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
435  m18_readdatavalid : in std_logic;
436  m18_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
437  m18_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
438  m18_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
439  m18_write : out std_logic;
440  m18_read : out std_logic;
441  m18_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
442  m18_debugaccess : out std_logic;
443  -- #####################################################################
444  -- Processor 19
445  s19_waitrequest : out std_logic;
446  s19_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
447  s19_readdatavalid : out std_logic;
448  s19_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
449  s19_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
450  s19_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
451  s19_write : in std_logic;
452  s19_read : in std_logic;
453  s19_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
454  s19_debugaccess : in std_logic;
455  m19_waitrequest : in std_logic;
456  m19_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
457  m19_readdatavalid : in std_logic;
458  m19_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
459  m19_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
460  m19_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
461  m19_write : out std_logic;
462  m19_read : out std_logic;
463  m19_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
464  m19_debugaccess : out std_logic;
465  -- #####################################################################
466  -- Processor 20
467  s20_waitrequest : out std_logic;
468  s20_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
469  s20_readdatavalid : out std_logic;
470  s20_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
471  s20_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
472  s20_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
473  s20_write : in std_logic;
474  s20_read : in std_logic;
475  s20_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
476  s20_debugaccess : in std_logic;
477  m20_waitrequest : in std_logic;
478  m20_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
479  m20_readdatavalid : in std_logic;
480  m20_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
481  m20_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
482  m20_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
483  m20_write : out std_logic;
484  m20_read : out std_logic;
485  m20_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
486  m20_debugaccess : out std_logic;
487  -- #####################################################################
488  -- Processor 21
489  s21_waitrequest : out std_logic;
490  s21_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
491  s21_readdatavalid : out std_logic;
492  s21_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
493  s21_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
494  s21_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
495  s21_write : in std_logic;
496  s21_read : in std_logic;
497  s21_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
498  s21_debugaccess : in std_logic;
499  m21_waitrequest : in std_logic;
500  m21_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
501  m21_readdatavalid : in std_logic;
502  m21_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
503  m21_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
504  m21_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
505  m21_write : out std_logic;
506  m21_read : out std_logic;
507  m21_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
508  m21_debugaccess : out std_logic;
509  -- #####################################################################
510  -- Processor 22
511  s22_waitrequest : out std_logic;
512  s22_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
513  s22_readdatavalid : out std_logic;
514  s22_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
515  s22_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
516  s22_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
517  s22_write : in std_logic;
518  s22_read : in std_logic;
519  s22_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
520  s22_debugaccess : in std_logic;
521  m22_waitrequest : in std_logic;
522  m22_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
523  m22_readdatavalid : in std_logic;
524  m22_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
525  m22_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
526  m22_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
527  m22_write : out std_logic;
528  m22_read : out std_logic;
529  m22_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
530  m22_debugaccess : out std_logic;
531  -- #####################################################################
532  -- Processor 23
533  s23_waitrequest : out std_logic;
534  s23_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
535  s23_readdatavalid : out std_logic;
536  s23_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
537  s23_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
538  s23_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
539  s23_write : in std_logic;
540  s23_read : in std_logic;
541  s23_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
542  s23_debugaccess : in std_logic;
543  m23_waitrequest : in std_logic;
544  m23_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
545  m23_readdatavalid : in std_logic;
546  m23_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
547  m23_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
548  m23_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
549  m23_write : out std_logic;
550  m23_read : out std_logic;
551  m23_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
552  m23_debugaccess : out std_logic;
553  -- #####################################################################
554  -- Processor 24
555  s24_waitrequest : out std_logic;
556  s24_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
557  s24_readdatavalid : out std_logic;
558  s24_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
559  s24_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
560  s24_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
561  s24_write : in std_logic;
562  s24_read : in std_logic;
563  s24_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
564  s24_debugaccess : in std_logic;
565  m24_waitrequest : in std_logic;
566  m24_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
567  m24_readdatavalid : in std_logic;
568  m24_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
569  m24_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
570  m24_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
571  m24_write : out std_logic;
572  m24_read : out std_logic;
573  m24_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
574  m24_debugaccess : out std_logic;
575  -- #####################################################################
576  -- Processor 25
577  s25_waitrequest : out std_logic;
578  s25_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
579  s25_readdatavalid : out std_logic;
580  s25_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
581  s25_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
582  s25_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
583  s25_write : in std_logic;
584  s25_read : in std_logic;
585  s25_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
586  s25_debugaccess : in std_logic;
587  m25_waitrequest : in std_logic;
588  m25_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
589  m25_readdatavalid : in std_logic;
590  m25_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
591  m25_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
592  m25_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
593  m25_write : out std_logic;
594  m25_read : out std_logic;
595  m25_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
596  m25_debugaccess : out std_logic;
597  -- #####################################################################
598  -- Processor 26
599  s26_waitrequest : out std_logic;
600  s26_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
601  s26_readdatavalid : out std_logic;
602  s26_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
603  s26_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
604  s26_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
605  s26_write : in std_logic;
606  s26_read : in std_logic;
607  s26_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
608  s26_debugaccess : in std_logic;
609  m26_waitrequest : in std_logic;
610  m26_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
611  m26_readdatavalid : in std_logic;
612  m26_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
613  m26_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
614  m26_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
615  m26_write : out std_logic;
616  m26_read : out std_logic;
617  m26_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
618  m26_debugaccess : out std_logic;
619  -- #####################################################################
620  -- Processor 27
621  s27_waitrequest : out std_logic;
622  s27_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
623  s27_readdatavalid : out std_logic;
624  s27_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
625  s27_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
626  s27_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
627  s27_write : in std_logic;
628  s27_read : in std_logic;
629  s27_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
630  s27_debugaccess : in std_logic;
631  m27_waitrequest : in std_logic;
632  m27_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
633  m27_readdatavalid : in std_logic;
634  m27_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
635  m27_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
636  m27_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
637  m27_write : out std_logic;
638  m27_read : out std_logic;
639  m27_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
640  m27_debugaccess : out std_logic;
641  -- #####################################################################
642  -- Processor 28
643  s28_waitrequest : out std_logic;
644  s28_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
645  s28_readdatavalid : out std_logic;
646  s28_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
647  s28_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
648  s28_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
649  s28_write : in std_logic;
650  s28_read : in std_logic;
651  s28_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
652  s28_debugaccess : in std_logic;
653  m28_waitrequest : in std_logic;
654  m28_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
655  m28_readdatavalid : in std_logic;
656  m28_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
657  m28_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
658  m28_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
659  m28_write : out std_logic;
660  m28_read : out std_logic;
661  m28_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
662  m28_debugaccess : out std_logic;
663  -- #####################################################################
664  -- Processor 29
665  s29_waitrequest : out std_logic;
666  s29_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
667  s29_readdatavalid : out std_logic;
668  s29_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
669  s29_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
670  s29_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
671  s29_write : in std_logic;
672  s29_read : in std_logic;
673  s29_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
674  s29_debugaccess : in std_logic;
675  m29_waitrequest : in std_logic;
676  m29_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
677  m29_readdatavalid : in std_logic;
678  m29_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
679  m29_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
680  m29_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
681  m29_write : out std_logic;
682  m29_read : out std_logic;
683  m29_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
684  m29_debugaccess : out std_logic;
685  -- #####################################################################
686  -- Processor 30
687  s30_waitrequest : out std_logic;
688  s30_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
689  s30_readdatavalid : out std_logic;
690  s30_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
691  s30_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
692  s30_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
693  s30_write : in std_logic;
694  s30_read : in std_logic;
695  s30_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
696  s30_debugaccess : in std_logic;
697  m30_waitrequest : in std_logic;
698  m30_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
699  m30_readdatavalid : in std_logic;
700  m30_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
701  m30_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
702  m30_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
703  m30_write : out std_logic;
704  m30_read : out std_logic;
705  m30_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
706  m30_debugaccess : out std_logic;
707  -- #####################################################################
708  -- Processor 31
709  s31_waitrequest : out std_logic;
710  s31_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
711  s31_readdatavalid : out std_logic;
712  s31_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
713  s31_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
714  s31_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
715  s31_write : in std_logic;
716  s31_read : in std_logic;
717  s31_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
718  s31_debugaccess : in std_logic;
719  m31_waitrequest : in std_logic;
720  m31_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
721  m31_readdatavalid : in std_logic;
722  m31_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
723  m31_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
724  m31_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
725  m31_write : out std_logic;
726  m31_read : out std_logic;
727  m31_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
728  m31_debugaccess : out std_logic;
729  -- #####################################################################
730  -- Processor 32
731  s32_waitrequest : out std_logic;
732  s32_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
733  s32_readdatavalid : out std_logic;
734  s32_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
735  s32_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
736  s32_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
737  s32_write : in std_logic;
738  s32_read : in std_logic;
739  s32_byteenable : in std_logic_vector(BYTEEN_WIDTH-1 downto 0);
740  s32_debugaccess : in std_logic;
741  m32_waitrequest : in std_logic;
742  m32_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
743  m32_readdatavalid : in std_logic;
744  m32_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0);
745  m32_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
746  m32_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
747  m32_write : out std_logic;
748  m32_read : out std_logic;
749  m32_byteenable : out std_logic_vector(BYTEEN_WIDTH-1 downto 0);
750  m32_debugaccess : out std_logic
751 
752  );
753 
754 end entity avalon_monitor;
755 
756 architecture AM1 of avalon_monitor is
757 
758 component STD_FIFO is
759  Generic (
760  constant DATA_WIDTH : positive := 8;
761  constant FIFO_DEPTH : positive := 256
762  );
763  Port (
764  CLK : in STD_LOGIC;
765  RST : in STD_LOGIC;
766  WriteEn : in STD_LOGIC;
767  DataIn : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
768  ReadEn : in STD_LOGIC;
769  DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
770  Empty : out STD_LOGIC;
771  Almost_Full : out STD_LOGIC;
772  Full : out STD_LOGIC
773  );
774 end component;
775 
776 
777  constant ADDR_FIFO_0 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(0, slave_AvalonMonitor_address'length));
778  constant ADDR_FIFO_1 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(1, slave_AvalonMonitor_address'length));
779  constant ADDR_FIFO_2 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(2, slave_AvalonMonitor_address'length));
780  constant ADDR_FIFO_3 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(3, slave_AvalonMonitor_address'length));
781  constant ADDR_FIFO_4 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(4, slave_AvalonMonitor_address'length));
782  constant ADDR_FIFO_5 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(5, slave_AvalonMonitor_address'length));
783  constant ADDR_FIFO_6 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(6, slave_AvalonMonitor_address'length));
784  constant ADDR_FIFO_7 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(7, slave_AvalonMonitor_address'length));
785  constant ADDR_FIFO_8 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(8, slave_AvalonMonitor_address'length));
786  constant ADDR_FIFO_9 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(9, slave_AvalonMonitor_address'length));
787  constant ADDR_FIFO_10 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(10, slave_AvalonMonitor_address'length));
788  constant ADDR_FIFO_11 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(11, slave_AvalonMonitor_address'length));
789  constant ADDR_FIFO_12 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(12, slave_AvalonMonitor_address'length));
790  constant ADDR_FIFO_13 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(13, slave_AvalonMonitor_address'length));
791  constant ADDR_FIFO_14 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(14, slave_AvalonMonitor_address'length));
792  constant ADDR_FIFO_15 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(15, slave_AvalonMonitor_address'length));
793  constant ADDR_FIFO_16 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(16, slave_AvalonMonitor_address'length));
794  constant ADDR_FIFO_17 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(17, slave_AvalonMonitor_address'length));
795  constant ADDR_FIFO_18 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(18, slave_AvalonMonitor_address'length));
796  constant ADDR_FIFO_19 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(19, slave_AvalonMonitor_address'length));
797  constant ADDR_FIFO_20 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(20, slave_AvalonMonitor_address'length));
798  constant ADDR_FIFO_21 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(21, slave_AvalonMonitor_address'length));
799  constant ADDR_FIFO_22 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(22, slave_AvalonMonitor_address'length));
800  constant ADDR_FIFO_23 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(23, slave_AvalonMonitor_address'length));
801  constant ADDR_FIFO_24 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(24, slave_AvalonMonitor_address'length));
802  constant ADDR_FIFO_25 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(25, slave_AvalonMonitor_address'length));
803  constant ADDR_FIFO_26 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(26, slave_AvalonMonitor_address'length));
804  constant ADDR_FIFO_27 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(27, slave_AvalonMonitor_address'length));
805  constant ADDR_FIFO_28 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(28, slave_AvalonMonitor_address'length));
806  constant ADDR_FIFO_29 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(29, slave_AvalonMonitor_address'length));
807  constant ADDR_FIFO_30 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(30, slave_AvalonMonitor_address'length));
808  constant ADDR_FIFO_31 : std_logic_vector(slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned(31, slave_AvalonMonitor_address'length));
809 
810 
811 
812  signal i1_address_prev , i1_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
813  signal i2_address_prev , i2_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
814  signal i3_address_prev , i3_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
815  signal i4_address_prev , i4_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
816  signal i5_address_prev , i5_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
817  signal i6_address_prev , i6_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
818  signal i7_address_prev , i7_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
819  signal i8_address_prev , i8_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
820  signal i9_address_prev , i9_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
821  signal i10_address_prev, i10_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
822  signal i11_address_prev, i11_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
823  signal i12_address_prev, i12_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
824  signal i13_address_prev, i13_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
825  signal i14_address_prev, i14_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
826  signal i15_address_prev, i15_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
827  signal i16_address_prev, i16_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
828  signal i17_address_prev, i17_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
829  signal i18_address_prev, i18_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
830  signal i19_address_prev, i19_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
831  signal i20_address_prev, i20_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
832  signal i21_address_prev, i21_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
833  signal i22_address_prev, i22_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
834  signal i23_address_prev, i23_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
835  signal i24_address_prev, i24_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
836  signal i25_address_prev, i25_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
837  signal i26_address_prev, i26_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
838  signal i27_address_prev, i27_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
839  signal i28_address_prev, i28_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
840  signal i29_address_prev, i29_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
841  signal i30_address_prev, i30_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
842  signal i31_address_prev, i31_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
843  signal i32_address_prev, i32_data_out : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
844 
845  signal slave_AvalonMonitor_readdata_int : STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0);
846 
847  signal i_frozzen : STD_LOGIC_VECTOR(32 downto 1);
848 
849  signal i1_empty, i1_full, i1_fifo_store, i1_read_fifo, i1_almost_full : STD_LOGIC;
850  signal i2_empty, i2_full, i2_fifo_store, i2_read_fifo, i2_almost_full : STD_LOGIC;
851  signal i3_empty, i3_full, i3_fifo_store, i3_read_fifo, i3_almost_full : STD_LOGIC;
852  signal i4_empty, i4_full, i4_fifo_store, i4_read_fifo, i4_almost_full : STD_LOGIC;
853  signal i5_empty, i5_full, i5_fifo_store, i5_read_fifo, i5_almost_full : STD_LOGIC;
854  signal i6_empty, i6_full, i6_fifo_store, i6_read_fifo, i6_almost_full : STD_LOGIC;
855  signal i7_empty, i7_full, i7_fifo_store, i7_read_fifo, i7_almost_full : STD_LOGIC;
856  signal i8_empty, i8_full, i8_fifo_store, i8_read_fifo, i8_almost_full : STD_LOGIC;
857  signal i9_empty, i9_full, i9_fifo_store, i9_read_fifo, i9_almost_full : STD_LOGIC;
858  signal i10_empty, i10_full, i10_fifo_store, i10_read_fifo, i10_almost_full : STD_LOGIC;
859  signal i11_empty, i11_full, i11_fifo_store, i11_read_fifo, i11_almost_full : STD_LOGIC;
860  signal i12_empty, i12_full, i12_fifo_store, i12_read_fifo, i12_almost_full : STD_LOGIC;
861  signal i13_empty, i13_full, i13_fifo_store, i13_read_fifo, i13_almost_full : STD_LOGIC;
862  signal i14_empty, i14_full, i14_fifo_store, i14_read_fifo, i14_almost_full : STD_LOGIC;
863  signal i15_empty, i15_full, i15_fifo_store, i15_read_fifo, i15_almost_full : STD_LOGIC;
864  signal i16_empty, i16_full, i16_fifo_store, i16_read_fifo, i16_almost_full : STD_LOGIC;
865  signal i17_empty, i17_full, i17_fifo_store, i17_read_fifo, i17_almost_full : STD_LOGIC;
866  signal i18_empty, i18_full, i18_fifo_store, i18_read_fifo, i18_almost_full : STD_LOGIC;
867  signal i19_empty, i19_full, i19_fifo_store, i19_read_fifo, i19_almost_full : STD_LOGIC;
868  signal i20_empty, i20_full, i20_fifo_store, i20_read_fifo, i20_almost_full : STD_LOGIC;
869  signal i21_empty, i21_full, i21_fifo_store, i21_read_fifo, i21_almost_full : STD_LOGIC;
870  signal i22_empty, i22_full, i22_fifo_store, i22_read_fifo, i22_almost_full : STD_LOGIC;
871  signal i23_empty, i23_full, i23_fifo_store, i23_read_fifo, i23_almost_full : STD_LOGIC;
872  signal i24_empty, i24_full, i24_fifo_store, i24_read_fifo, i24_almost_full : STD_LOGIC;
873  signal i25_empty, i25_full, i25_fifo_store, i25_read_fifo, i25_almost_full : STD_LOGIC;
874  signal i26_empty, i26_full, i26_fifo_store, i26_read_fifo, i26_almost_full : STD_LOGIC;
875  signal i27_empty, i27_full, i27_fifo_store, i27_read_fifo, i27_almost_full : STD_LOGIC;
876  signal i28_empty, i28_full, i28_fifo_store, i28_read_fifo, i28_almost_full : STD_LOGIC;
877  signal i29_empty, i29_full, i29_fifo_store, i29_read_fifo, i29_almost_full : STD_LOGIC;
878  signal i30_empty, i30_full, i30_fifo_store, i30_read_fifo, i30_almost_full : STD_LOGIC;
879  signal i31_empty, i31_full, i31_fifo_store, i31_read_fifo, i31_almost_full : STD_LOGIC;
880  signal i32_empty, i32_full, i32_fifo_store, i32_read_fifo, i32_almost_full : STD_LOGIC;
881 
882 
883  -- signal counter : signed(15 downto 0);
884  signal prev_AvalonMonitor_read : std_logic;
885  signal prev_AvalonMonitor_address : std_logic_vector(slave_AvalonMonitor_address'left downto 0);
886 
887  -- Control registers
888  -- Bit 0: if 1 then frozen when fifo is full, 0 works normally
889  -- Bit 1: if 1 then frozen
890  -- Bit 2: if 1 then read fifo until it is empty
891  signal R_CTRL : STD_LOGIC_VECTOR(31 downto 0);
892 
893 
894 begin
895  process(reset, clk) is
896  variable frozen_out_i : STD_LOGIC;
897  begin
898  frozen_out_i := '0';
899  for i in 1 to NProcessors loop
900  frozen_out_i := frozen_out_i or i_frozzen(i);
901  end loop;
902  frozen_avalon_monitor <= frozen_out_i;
903  end process;
904  -- #######################################################################################################################
905 
906  u1: STD_FIFO
907  generic map (
908  DATA_WIDTH => ADDRESS_WIDTH,
909  FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH )
910  port map (
911  CLK => clk,
912  RST => reset,
913  WriteEn => i1_fifo_store,
914  DataIn => s1_address,
915  ReadEn => i1_read_fifo,
916  DataOut => i1_data_out,
917  Empty => i1_empty,
918  Almost_Full => i1_almost_full ,
919  Full => i1_full );
920 
921  i1_fifo_store <= '0' when i1_full = '1' or R_CTRL(2) = '1' else
922  '1' when i1_address_prev /= s1_address and s1_read = '1' else
923  '0';
924  i1_read_fifo <= '1' when i1_empty = '0' and R_CTRL(2) = '1' else
925  '1' when i1_almost_full = '1' and R_CTRL(0) = '0' else
926  '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_0 else
927  '0';
928 
929  i_frozzen(1) <= '1' when ((i1_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i1_address_prev /= s1_address and s1_read = '1' else
930  '0';
931 
932  -- #######################################################################################################################
933 
934  u2: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i2_fifo_store, DataIn => s2_address, ReadEn => i2_read_fifo, DataOut => i2_data_out, Empty => i2_empty, Almost_Full => i2_almost_full , Full => i2_full );
935  u3: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i3_fifo_store, DataIn => s3_address, ReadEn => i3_read_fifo, DataOut => i3_data_out, Empty => i3_empty, Almost_Full => i3_almost_full , Full => i3_full );
936  u4: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i4_fifo_store, DataIn => s4_address, ReadEn => i4_read_fifo, DataOut => i4_data_out, Empty => i4_empty, Almost_Full => i4_almost_full , Full => i4_full );
937  u5: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i5_fifo_store, DataIn => s5_address, ReadEn => i5_read_fifo, DataOut => i5_data_out, Empty => i5_empty, Almost_Full => i5_almost_full , Full => i5_full );
938  u6: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i6_fifo_store, DataIn => s6_address, ReadEn => i6_read_fifo, DataOut => i6_data_out, Empty => i6_empty, Almost_Full => i6_almost_full , Full => i6_full );
939  u7: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i7_fifo_store, DataIn => s7_address, ReadEn => i7_read_fifo, DataOut => i7_data_out, Empty => i7_empty, Almost_Full => i7_almost_full , Full => i7_full );
940  u8: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i8_fifo_store, DataIn => s8_address, ReadEn => i8_read_fifo, DataOut => i8_data_out, Empty => i8_empty, Almost_Full => i8_almost_full , Full => i8_full );
941  u9: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i9_fifo_store, DataIn => s9_address, ReadEn => i9_read_fifo, DataOut => i9_data_out, Empty => i9_empty, Almost_Full => i9_almost_full , Full => i9_full );
942  u10: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i10_fifo_store, DataIn => s10_address, ReadEn => i10_read_fifo, DataOut => i10_data_out, Empty => i10_empty, Almost_Full => i10_almost_full, Full => i10_full );
943  u11: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i11_fifo_store, DataIn => s11_address, ReadEn => i11_read_fifo, DataOut => i11_data_out, Empty => i11_empty, Almost_Full => i11_almost_full, Full => i11_full );
944  u12: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i12_fifo_store, DataIn => s12_address, ReadEn => i12_read_fifo, DataOut => i12_data_out, Empty => i12_empty, Almost_Full => i12_almost_full, Full => i12_full );
945  u13: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i13_fifo_store, DataIn => s13_address, ReadEn => i13_read_fifo, DataOut => i13_data_out, Empty => i13_empty, Almost_Full => i13_almost_full, Full => i13_full );
946  u14: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i14_fifo_store, DataIn => s14_address, ReadEn => i14_read_fifo, DataOut => i14_data_out, Empty => i14_empty, Almost_Full => i14_almost_full, Full => i14_full );
947  u15: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i15_fifo_store, DataIn => s15_address, ReadEn => i15_read_fifo, DataOut => i15_data_out, Empty => i15_empty, Almost_Full => i15_almost_full, Full => i15_full );
948  u16: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i16_fifo_store, DataIn => s16_address, ReadEn => i16_read_fifo, DataOut => i16_data_out, Empty => i16_empty, Almost_Full => i16_almost_full, Full => i16_full );
949  u17: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i17_fifo_store, DataIn => s17_address, ReadEn => i17_read_fifo, DataOut => i17_data_out, Empty => i17_empty, Almost_Full => i17_almost_full, Full => i17_full );
950  u18: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i18_fifo_store, DataIn => s18_address, ReadEn => i18_read_fifo, DataOut => i18_data_out, Empty => i18_empty, Almost_Full => i18_almost_full, Full => i18_full );
951  u19: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i19_fifo_store, DataIn => s19_address, ReadEn => i19_read_fifo, DataOut => i19_data_out, Empty => i19_empty, Almost_Full => i19_almost_full, Full => i19_full );
952  u20: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i20_fifo_store, DataIn => s20_address, ReadEn => i20_read_fifo, DataOut => i20_data_out, Empty => i20_empty, Almost_Full => i20_almost_full, Full => i20_full );
953  u21: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i21_fifo_store, DataIn => s21_address, ReadEn => i21_read_fifo, DataOut => i21_data_out, Empty => i21_empty, Almost_Full => i21_almost_full, Full => i21_full );
954  u22: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i22_fifo_store, DataIn => s22_address, ReadEn => i22_read_fifo, DataOut => i22_data_out, Empty => i22_empty, Almost_Full => i22_almost_full, Full => i22_full );
955  u23: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i23_fifo_store, DataIn => s23_address, ReadEn => i23_read_fifo, DataOut => i23_data_out, Empty => i23_empty, Almost_Full => i23_almost_full, Full => i23_full );
956  u24: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i24_fifo_store, DataIn => s24_address, ReadEn => i24_read_fifo, DataOut => i24_data_out, Empty => i24_empty, Almost_Full => i24_almost_full, Full => i24_full );
957  u25: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i25_fifo_store, DataIn => s25_address, ReadEn => i25_read_fifo, DataOut => i25_data_out, Empty => i25_empty, Almost_Full => i25_almost_full, Full => i25_full );
958  u26: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i26_fifo_store, DataIn => s26_address, ReadEn => i26_read_fifo, DataOut => i26_data_out, Empty => i26_empty, Almost_Full => i26_almost_full, Full => i26_full );
959  u27: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i27_fifo_store, DataIn => s27_address, ReadEn => i27_read_fifo, DataOut => i27_data_out, Empty => i27_empty, Almost_Full => i27_almost_full, Full => i27_full );
960  u28: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i28_fifo_store, DataIn => s28_address, ReadEn => i28_read_fifo, DataOut => i28_data_out, Empty => i28_empty, Almost_Full => i28_almost_full, Full => i28_full );
961  u29: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i29_fifo_store, DataIn => s29_address, ReadEn => i29_read_fifo, DataOut => i29_data_out, Empty => i29_empty, Almost_Full => i29_almost_full, Full => i29_full );
962  u30: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i30_fifo_store, DataIn => s30_address, ReadEn => i30_read_fifo, DataOut => i30_data_out, Empty => i30_empty, Almost_Full => i30_almost_full, Full => i30_full );
963  u31: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i31_fifo_store, DataIn => s31_address, ReadEn => i31_read_fifo, DataOut => i31_data_out, Empty => i31_empty, Almost_Full => i31_almost_full, Full => i31_full );
964  u32: STD_FIFO generic map ( DATA_WIDTH => ADDRESS_WIDTH, FIFO_DEPTH => AVALON_DATA_FIFO_DEPTH ) port map ( CLK => clk, RST => reset, WriteEn => i32_fifo_store, DataIn => s32_address, ReadEn => i32_read_fifo, DataOut => i32_data_out, Empty => i32_empty, Almost_Full => i32_almost_full, Full => i32_full );
965 
966 
967 
968 
969  i2_fifo_store <= '0' when i2_full = '1' or R_CTRL(2) = '1' else '1' when i2_address_prev /= s2_address and s2_read = '1' else '0';
970  i3_fifo_store <= '0' when i3_full = '1' or R_CTRL(2) = '1' else '1' when i3_address_prev /= s3_address and s3_read = '1' else '0';
971  i4_fifo_store <= '0' when i4_full = '1' or R_CTRL(2) = '1' else '1' when i4_address_prev /= s4_address and s4_read = '1' else '0';
972  i5_fifo_store <= '0' when i5_full = '1' or R_CTRL(2) = '1' else '1' when i5_address_prev /= s5_address and s5_read = '1' else '0';
973  i6_fifo_store <= '0' when i6_full = '1' or R_CTRL(2) = '1' else '1' when i6_address_prev /= s6_address and s6_read = '1' else '0';
974  i7_fifo_store <= '0' when i7_full = '1' or R_CTRL(2) = '1' else '1' when i7_address_prev /= s7_address and s7_read = '1' else '0';
975  i8_fifo_store <= '0' when i8_full = '1' or R_CTRL(2) = '1' else '1' when i8_address_prev /= s8_address and s8_read = '1' else '0';
976  i9_fifo_store <= '0' when i9_full = '1' or R_CTRL(2) = '1' else '1' when i9_address_prev /= s9_address and s9_read = '1' else '0';
977  i10_fifo_store <= '0' when i10_full = '1' or R_CTRL(2) = '1' else '1' when i10_address_prev /= s10_address and s10_read = '1' else '0';
978  i11_fifo_store <= '0' when i11_full = '1' or R_CTRL(2) = '1' else '1' when i11_address_prev /= s11_address and s11_read = '1' else '0';
979  i12_fifo_store <= '0' when i12_full = '1' or R_CTRL(2) = '1' else '1' when i12_address_prev /= s12_address and s12_read = '1' else '0';
980  i13_fifo_store <= '0' when i13_full = '1' or R_CTRL(2) = '1' else '1' when i13_address_prev /= s13_address and s13_read = '1' else '0';
981  i14_fifo_store <= '0' when i14_full = '1' or R_CTRL(2) = '1' else '1' when i14_address_prev /= s14_address and s14_read = '1' else '0';
982  i15_fifo_store <= '0' when i15_full = '1' or R_CTRL(2) = '1' else '1' when i15_address_prev /= s15_address and s15_read = '1' else '0';
983  i16_fifo_store <= '0' when i16_full = '1' or R_CTRL(2) = '1' else '1' when i16_address_prev /= s16_address and s16_read = '1' else '0';
984  i17_fifo_store <= '0' when i17_full = '1' or R_CTRL(2) = '1' else '1' when i17_address_prev /= s17_address and s17_read = '1' else '0';
985  i18_fifo_store <= '0' when i18_full = '1' or R_CTRL(2) = '1' else '1' when i18_address_prev /= s18_address and s18_read = '1' else '0';
986  i19_fifo_store <= '0' when i19_full = '1' or R_CTRL(2) = '1' else '1' when i19_address_prev /= s19_address and s19_read = '1' else '0';
987  i20_fifo_store <= '0' when i20_full = '1' or R_CTRL(2) = '1' else '1' when i20_address_prev /= s20_address and s20_read = '1' else '0';
988  i21_fifo_store <= '0' when i21_full = '1' or R_CTRL(2) = '1' else '1' when i21_address_prev /= s21_address and s21_read = '1' else '0';
989  i22_fifo_store <= '0' when i22_full = '1' or R_CTRL(2) = '1' else '1' when i22_address_prev /= s22_address and s22_read = '1' else '0';
990  i23_fifo_store <= '0' when i23_full = '1' or R_CTRL(2) = '1' else '1' when i23_address_prev /= s23_address and s23_read = '1' else '0';
991  i24_fifo_store <= '0' when i24_full = '1' or R_CTRL(2) = '1' else '1' when i24_address_prev /= s24_address and s24_read = '1' else '0';
992  i25_fifo_store <= '0' when i25_full = '1' or R_CTRL(2) = '1' else '1' when i25_address_prev /= s25_address and s25_read = '1' else '0';
993  i26_fifo_store <= '0' when i26_full = '1' or R_CTRL(2) = '1' else '1' when i26_address_prev /= s26_address and s26_read = '1' else '0';
994  i27_fifo_store <= '0' when i27_full = '1' or R_CTRL(2) = '1' else '1' when i27_address_prev /= s27_address and s27_read = '1' else '0';
995  i28_fifo_store <= '0' when i28_full = '1' or R_CTRL(2) = '1' else '1' when i28_address_prev /= s28_address and s28_read = '1' else '0';
996  i29_fifo_store <= '0' when i29_full = '1' or R_CTRL(2) = '1' else '1' when i29_address_prev /= s29_address and s29_read = '1' else '0';
997  i30_fifo_store <= '0' when i30_full = '1' or R_CTRL(2) = '1' else '1' when i30_address_prev /= s30_address and s30_read = '1' else '0';
998  i31_fifo_store <= '0' when i31_full = '1' or R_CTRL(2) = '1' else '1' when i31_address_prev /= s31_address and s31_read = '1' else '0';
999  i32_fifo_store <= '0' when i32_full = '1' or R_CTRL(2) = '1' else '1' when i32_address_prev /= s32_address and s32_read = '1' else '0';
1000 
1001  Edge_logic:
1002  process(reset, clk) is
1003  begin
1004  if (reset = '1') then
1005  i1_address_prev <= (others => '0');
1006  i2_address_prev <= (others => '0');
1007  i3_address_prev <= (others => '0');
1008  i4_address_prev <= (others => '0');
1009  i5_address_prev <= (others => '0');
1010  i6_address_prev <= (others => '0');
1011  i7_address_prev <= (others => '0');
1012  i8_address_prev <= (others => '0');
1013  i9_address_prev <= (others => '0');
1014  i10_address_prev <= (others => '0');
1015  i11_address_prev <= (others => '0');
1016  i12_address_prev <= (others => '0');
1017  i13_address_prev <= (others => '0');
1018  i14_address_prev <= (others => '0');
1019  i15_address_prev <= (others => '0');
1020  i16_address_prev <= (others => '0');
1021  i17_address_prev <= (others => '0');
1022  i18_address_prev <= (others => '0');
1023  i19_address_prev <= (others => '0');
1024  i20_address_prev <= (others => '0');
1025  i21_address_prev <= (others => '0');
1026  i22_address_prev <= (others => '0');
1027  i23_address_prev <= (others => '0');
1028  i24_address_prev <= (others => '0');
1029  i25_address_prev <= (others => '0');
1030  i26_address_prev <= (others => '0');
1031  i27_address_prev <= (others => '0');
1032  i28_address_prev <= (others => '0');
1033  i29_address_prev <= (others => '0');
1034  i30_address_prev <= (others => '0');
1035  i31_address_prev <= (others => '0');
1036  i32_address_prev <= (others => '0');
1037 
1038  prev_AvalonMonitor_address <= (others => '0');
1039  prev_AvalonMonitor_read <= '0';
1040  elsif (clk'event and clk = '1') then
1041  prev_AvalonMonitor_read <= slave_AvalonMonitor_read;
1042  prev_AvalonMonitor_address <= slave_AvalonMonitor_address;
1043  if i1_full = '0' and s1_read = '1' then i1_address_prev <= s1_address; end if;
1044  if i2_full = '0' and s2_read = '1' then i2_address_prev <= s2_address; end if;
1045  if i3_full = '0' and s3_read = '1' then i3_address_prev <= s3_address; end if;
1046  if i4_full = '0' and s4_read = '1' then i4_address_prev <= s4_address; end if;
1047  if i5_full = '0' and s5_read = '1' then i5_address_prev <= s5_address; end if;
1048  if i6_full = '0' and s6_read = '1' then i6_address_prev <= s6_address; end if;
1049  if i7_full = '0' and s7_read = '1' then i7_address_prev <= s7_address; end if;
1050  if i8_full = '0' and s8_read = '1' then i8_address_prev <= s8_address; end if;
1051  if i9_full = '0' and s9_read = '1' then i9_address_prev <= s9_address; end if;
1052  if i10_full = '0' and s10_read = '1' then i10_address_prev <= s10_address; end if;
1053  if i11_full = '0' and s11_read = '1' then i11_address_prev <= s11_address; end if;
1054  if i12_full = '0' and s12_read = '1' then i12_address_prev <= s12_address; end if;
1055  if i13_full = '0' and s13_read = '1' then i13_address_prev <= s13_address; end if;
1056  if i14_full = '0' and s14_read = '1' then i14_address_prev <= s14_address; end if;
1057  if i15_full = '0' and s15_read = '1' then i15_address_prev <= s15_address; end if;
1058  if i16_full = '0' and s16_read = '1' then i16_address_prev <= s16_address; end if;
1059  if i17_full = '0' and s17_read = '1' then i17_address_prev <= s17_address; end if;
1060  if i18_full = '0' and s18_read = '1' then i18_address_prev <= s18_address; end if;
1061  if i19_full = '0' and s19_read = '1' then i19_address_prev <= s19_address; end if;
1062  if i20_full = '0' and s20_read = '1' then i20_address_prev <= s20_address; end if;
1063  if i21_full = '0' and s21_read = '1' then i21_address_prev <= s21_address; end if;
1064  if i22_full = '0' and s22_read = '1' then i22_address_prev <= s22_address; end if;
1065  if i23_full = '0' and s23_read = '1' then i23_address_prev <= s23_address; end if;
1066  if i24_full = '0' and s24_read = '1' then i24_address_prev <= s24_address; end if;
1067  if i25_full = '0' and s25_read = '1' then i25_address_prev <= s25_address; end if;
1068  if i26_full = '0' and s26_read = '1' then i26_address_prev <= s26_address; end if;
1069  if i27_full = '0' and s27_read = '1' then i27_address_prev <= s27_address; end if;
1070  if i28_full = '0' and s28_read = '1' then i28_address_prev <= s28_address; end if;
1071  if i29_full = '0' and s29_read = '1' then i29_address_prev <= s29_address; end if;
1072  if i30_full = '0' and s30_read = '1' then i30_address_prev <= s30_address; end if;
1073  if i31_full = '0' and s31_read = '1' then i31_address_prev <= s31_address; end if;
1074  if i32_full = '0' and s32_read = '1' then i32_address_prev <= s32_address; end if;
1075  end if;
1076  end process;
1077 
1078  -- Counter_proccess:
1079  -- process(reset, clk) is
1080  -- begin
1081  -- if (reset = '1') then
1082  -- counter <= (others => '0');
1083  -- elsif (clk'event and clk = '1') then
1084  -- counter <= counter + 1;
1085  -- end if;
1086  -- end process;
1087 
1088 
1089  i2_read_fifo <= '1' when i2_empty = '0' and R_CTRL(2) = '1' else '1' when i2_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_1 else '0';
1090  i3_read_fifo <= '1' when i3_empty = '0' and R_CTRL(2) = '1' else '1' when i3_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_2 else '0';
1091  i4_read_fifo <= '1' when i4_empty = '0' and R_CTRL(2) = '1' else '1' when i4_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_3 else '0';
1092  i5_read_fifo <= '1' when i5_empty = '0' and R_CTRL(2) = '1' else '1' when i5_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_4 else '0';
1093  i6_read_fifo <= '1' when i6_empty = '0' and R_CTRL(2) = '1' else '1' when i6_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_5 else '0';
1094  i7_read_fifo <= '1' when i7_empty = '0' and R_CTRL(2) = '1' else '1' when i7_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_6 else '0';
1095  i8_read_fifo <= '1' when i8_empty = '0' and R_CTRL(2) = '1' else '1' when i8_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_7 else '0';
1096  i9_read_fifo <= '1' when i9_empty = '0' and R_CTRL(2) = '1' else '1' when i9_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_8 else '0';
1097  i10_read_fifo <= '1' when i10_empty = '0' and R_CTRL(2) = '1' else '1' when i10_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_9 else '0';
1098  i11_read_fifo <= '1' when i11_empty = '0' and R_CTRL(2) = '1' else '1' when i11_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_10 else '0';
1099  i12_read_fifo <= '1' when i12_empty = '0' and R_CTRL(2) = '1' else '1' when i12_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_11 else '0';
1100  i13_read_fifo <= '1' when i13_empty = '0' and R_CTRL(2) = '1' else '1' when i13_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_12 else '0';
1101  i14_read_fifo <= '1' when i14_empty = '0' and R_CTRL(2) = '1' else '1' when i14_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_13 else '0';
1102  i15_read_fifo <= '1' when i15_empty = '0' and R_CTRL(2) = '1' else '1' when i15_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_14 else '0';
1103  i16_read_fifo <= '1' when i16_empty = '0' and R_CTRL(2) = '1' else '1' when i16_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_15 else '0';
1104  i17_read_fifo <= '1' when i17_empty = '0' and R_CTRL(2) = '1' else '1' when i17_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_16 else '0';
1105  i18_read_fifo <= '1' when i18_empty = '0' and R_CTRL(2) = '1' else '1' when i18_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_17 else '0';
1106  i19_read_fifo <= '1' when i19_empty = '0' and R_CTRL(2) = '1' else '1' when i19_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_18 else '0';
1107  i20_read_fifo <= '1' when i20_empty = '0' and R_CTRL(2) = '1' else '1' when i20_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_19 else '0';
1108  i21_read_fifo <= '1' when i21_empty = '0' and R_CTRL(2) = '1' else '1' when i21_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_10 else '0';
1109  i22_read_fifo <= '1' when i22_empty = '0' and R_CTRL(2) = '1' else '1' when i22_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_21 else '0';
1110  i23_read_fifo <= '1' when i23_empty = '0' and R_CTRL(2) = '1' else '1' when i23_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_22 else '0';
1111  i24_read_fifo <= '1' when i24_empty = '0' and R_CTRL(2) = '1' else '1' when i24_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_23 else '0';
1112  i25_read_fifo <= '1' when i25_empty = '0' and R_CTRL(2) = '1' else '1' when i25_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_24 else '0';
1113  i26_read_fifo <= '1' when i26_empty = '0' and R_CTRL(2) = '1' else '1' when i26_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_25 else '0';
1114  i27_read_fifo <= '1' when i27_empty = '0' and R_CTRL(2) = '1' else '1' when i27_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_26 else '0';
1115  i28_read_fifo <= '1' when i28_empty = '0' and R_CTRL(2) = '1' else '1' when i28_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_27 else '0';
1116  i29_read_fifo <= '1' when i29_empty = '0' and R_CTRL(2) = '1' else '1' when i29_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_28 else '0';
1117  i30_read_fifo <= '1' when i30_empty = '0' and R_CTRL(2) = '1' else '1' when i30_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_29 else '0';
1118  i31_read_fifo <= '1' when i31_empty = '0' and R_CTRL(2) = '1' else '1' when i31_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_30 else '0';
1119  i32_read_fifo <= '1' when i32_empty = '0' and R_CTRL(2) = '1' else '1' when i32_almost_full = '1' and R_CTRL(0) = '0' else '1' when slave_AvalonMonitor_read = '0' and prev_AvalonMonitor_read = '1' and prev_AvalonMonitor_address = ADDR_FIFO_31 else '0';
1120 
1121  i_frozzen(2) <= '1' when ((i2_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i2_address_prev /= s2_address and s2_read = '1' else '0';
1122  i_frozzen(3) <= '1' when ((i3_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i3_address_prev /= s3_address and s3_read = '1' else '0';
1123  i_frozzen(4) <= '1' when ((i4_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i4_address_prev /= s4_address and s4_read = '1' else '0';
1124  i_frozzen(5) <= '1' when ((i5_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i5_address_prev /= s5_address and s5_read = '1' else '0';
1125  i_frozzen(6) <= '1' when ((i6_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i6_address_prev /= s6_address and s6_read = '1' else '0';
1126  i_frozzen(7) <= '1' when ((i7_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i7_address_prev /= s7_address and s7_read = '1' else '0';
1127  i_frozzen(8) <= '1' when ((i8_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i8_address_prev /= s8_address and s8_read = '1' else '0';
1128  i_frozzen(9) <= '1' when ((i9_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i9_address_prev /= s9_address and s9_read = '1' else '0';
1129  i_frozzen(10) <= '1' when ((i10_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i10_address_prev /= s10_address and s10_read = '1' else '0';
1130  i_frozzen(11) <= '1' when ((i11_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i11_address_prev /= s11_address and s11_read = '1' else '0';
1131  i_frozzen(12) <= '1' when ((i12_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i12_address_prev /= s12_address and s12_read = '1' else '0';
1132  i_frozzen(13) <= '1' when ((i13_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i13_address_prev /= s13_address and s13_read = '1' else '0';
1133  i_frozzen(14) <= '1' when ((i14_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i14_address_prev /= s14_address and s14_read = '1' else '0';
1134  i_frozzen(15) <= '1' when ((i15_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i15_address_prev /= s15_address and s15_read = '1' else '0';
1135  i_frozzen(16) <= '1' when ((i16_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i16_address_prev /= s16_address and s16_read = '1' else '0';
1136  i_frozzen(17) <= '1' when ((i17_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i17_address_prev /= s17_address and s17_read = '1' else '0';
1137  i_frozzen(18) <= '1' when ((i18_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i18_address_prev /= s18_address and s18_read = '1' else '0';
1138  i_frozzen(19) <= '1' when ((i19_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i19_address_prev /= s19_address and s19_read = '1' else '0';
1139  i_frozzen(20) <= '1' when ((i20_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i20_address_prev /= s20_address and s20_read = '1' else '0';
1140  i_frozzen(21) <= '1' when ((i21_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i21_address_prev /= s21_address and s21_read = '1' else '0';
1141  i_frozzen(22) <= '1' when ((i22_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i22_address_prev /= s22_address and s22_read = '1' else '0';
1142  i_frozzen(23) <= '1' when ((i23_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i23_address_prev /= s23_address and s23_read = '1' else '0';
1143  i_frozzen(24) <= '1' when ((i24_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i24_address_prev /= s24_address and s24_read = '1' else '0';
1144  i_frozzen(25) <= '1' when ((i25_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i25_address_prev /= s25_address and s25_read = '1' else '0';
1145  i_frozzen(26) <= '1' when ((i26_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i26_address_prev /= s26_address and s26_read = '1' else '0';
1146  i_frozzen(27) <= '1' when ((i27_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i27_address_prev /= s27_address and s27_read = '1' else '0';
1147  i_frozzen(28) <= '1' when ((i28_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i28_address_prev /= s28_address and s28_read = '1' else '0';
1148  i_frozzen(29) <= '1' when ((i29_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i29_address_prev /= s29_address and s29_read = '1' else '0';
1149  i_frozzen(30) <= '1' when ((i30_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i30_address_prev /= s30_address and s30_read = '1' else '0';
1150  i_frozzen(31) <= '1' when ((i31_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i31_address_prev /= s31_address and s31_read = '1' else '0';
1151  i_frozzen(32) <= '1' when ((i32_full = '1' and R_CTRL(0) = '1') or R_CTRL(1) = '1') and i32_address_prev /= s32_address and s32_read = '1' else '0';
1152 
1153 
1154 Slave_Avalon_Read:
1155  WITH slave_AvalonMonitor_address SELECT
1156  slave_AvalonMonitor_readdata_int <= i1_data_out when ADDR_FIFO_0,
1157  i2_data_out when ADDR_FIFO_1,
1158  i3_data_out when ADDR_FIFO_2,
1159  i4_data_out when ADDR_FIFO_3,
1160  i5_data_out when ADDR_FIFO_4,
1161  i6_data_out when ADDR_FIFO_5,
1162  i7_data_out when ADDR_FIFO_6,
1163  i8_data_out when ADDR_FIFO_7,
1164  i9_data_out when ADDR_FIFO_8,
1165  i10_data_out when ADDR_FIFO_9,
1166  i11_data_out when ADDR_FIFO_10,
1167  i12_data_out when ADDR_FIFO_11,
1168  i13_data_out when ADDR_FIFO_12,
1169  i14_data_out when ADDR_FIFO_13,
1170  i15_data_out when ADDR_FIFO_14,
1171  i16_data_out when ADDR_FIFO_15,
1172  i17_data_out when ADDR_FIFO_16,
1173  i18_data_out when ADDR_FIFO_17,
1174  i19_data_out when ADDR_FIFO_18,
1175  i20_data_out when ADDR_FIFO_19,
1176  i21_data_out when ADDR_FIFO_20,
1177  i22_data_out when ADDR_FIFO_21,
1178  i23_data_out when ADDR_FIFO_22,
1179  i24_data_out when ADDR_FIFO_23,
1180  i25_data_out when ADDR_FIFO_24,
1181  i26_data_out when ADDR_FIFO_25,
1182  i27_data_out when ADDR_FIFO_26,
1183  i28_data_out when ADDR_FIFO_27,
1184  i29_data_out when ADDR_FIFO_28,
1185  i30_data_out when ADDR_FIFO_29,
1186  i31_data_out when ADDR_FIFO_30,
1187  i32_data_out when ADDR_FIFO_31,
1188  (others => '0') when others;
1189 
1190 Read_data: process (slave_AvalonMonitor_readdata_int) is
1191  begin
1192  slave_AvalonMonitor_readdata <= (others => '0');
1193  slave_AvalonMonitor_readdata(ADDRESS_WIDTH - 1 downto 0) <= slave_AvalonMonitor_readdata_int;
1194  end process;
1195 
1196 Control_register:
1197  process(reset, clk) is
1198  begin
1199  if (reset = '1') then
1200  R_CTRL <= (others => '0');
1201  elsif (clk'event and clk = '1') then
1202  if (slave_AvalonMonitor_write = '1' and slave_AvalonMonitor_address = ADDR_FIFO_0) then
1203  R_CTRL <= slave_AvalonMonitor_writedata;
1204  end if;
1205  end if;
1206  end process;
1207 
1208 
1209  m1_burstcount <= s1_burstcount;
1210  m1_writedata <= s1_writedata;
1211  m1_address <= s1_address;
1212  m1_write <= s1_write;
1213  m1_read <= s1_read when i_frozzen(1) = '0' else '0';
1214  m1_byteenable <= s1_byteenable;
1215  m1_debugaccess <= s1_debugaccess;
1216  s1_waitrequest <= m1_waitrequest when i_frozzen(1) = '0' else '1';
1217  s1_readdatavalid <= m1_readdatavalid;
1218  s1_readdata <= m1_readdata;
1219 
1220  m2_burstcount <= s2_burstcount;
1221  m2_writedata <= s2_writedata;
1222  m2_address <= s2_address;
1223  m2_write <= s2_write;
1224  m2_read <= s2_read when i_frozzen(2) = '0' else '0';
1225  m2_byteenable <= s2_byteenable;
1226  m2_debugaccess <= s2_debugaccess;
1227  s2_waitrequest <= m2_waitrequest when i_frozzen(2) = '0' else '1';
1228  s2_readdatavalid <= m2_readdatavalid;
1229  s2_readdata <= m2_readdata;
1230 
1231  m3_burstcount <= s3_burstcount;
1232  m3_writedata <= s3_writedata;
1233  m3_address <= s3_address;
1234  m3_write <= s3_write;
1235  m3_read <= s3_read when i_frozzen(3) = '0' else '0';
1236  m3_byteenable <= s3_byteenable;
1237  m3_debugaccess <= s3_debugaccess;
1238  s3_waitrequest <= m3_waitrequest when i_frozzen(3) = '0' else '1';
1239  s3_readdatavalid <= m3_readdatavalid;
1240  s3_readdata <= m3_readdata;
1241 
1242  m4_burstcount <= s4_burstcount;
1243  m4_writedata <= s4_writedata;
1244  m4_address <= s4_address;
1245  m4_write <= s4_write;
1246  m4_read <= s4_read when i_frozzen(4) = '0' else '0';
1247  m4_byteenable <= s4_byteenable;
1248  m4_debugaccess <= s4_debugaccess;
1249  s4_waitrequest <= m4_waitrequest when i_frozzen(4) = '0' else '1';
1250  s4_readdatavalid <= m4_readdatavalid;
1251  s4_readdata <= m4_readdata;
1252 
1253  m5_burstcount <= s5_burstcount;
1254  m5_writedata <= s5_writedata;
1255  m5_address <= s5_address;
1256  m5_write <= s5_write;
1257  m5_read <= s5_read when i_frozzen(5) = '0' else '0';
1258  m5_byteenable <= s5_byteenable;
1259  m5_debugaccess <= s5_debugaccess;
1260  s5_waitrequest <= m5_waitrequest when i_frozzen(5) = '0' else '1';
1261  s5_readdatavalid <= m5_readdatavalid;
1262  s5_readdata <= m5_readdata;
1263 
1264  m6_burstcount <= s6_burstcount;
1265  m6_writedata <= s6_writedata;
1266  m6_address <= s6_address;
1267  m6_write <= s6_write;
1268  m6_read <= s6_read when i_frozzen(6) = '0' else '0';
1269  m6_byteenable <= s6_byteenable;
1270  m6_debugaccess <= s6_debugaccess;
1271  s6_waitrequest <= m6_waitrequest when i_frozzen(6) = '0' else '1';
1272  s6_readdatavalid <= m6_readdatavalid;
1273  s6_readdata <= m6_readdata;
1274 
1275  m7_burstcount <= s7_burstcount;
1276  m7_writedata <= s7_writedata;
1277  m7_address <= s7_address;
1278  m7_write <= s7_write;
1279  m7_read <= s7_read when i_frozzen(7) = '0' else '0';
1280  m7_byteenable <= s7_byteenable;
1281  m7_debugaccess <= s7_debugaccess;
1282  s7_waitrequest <= m7_waitrequest when i_frozzen(7) = '0' else '1';
1283  s7_readdatavalid <= m7_readdatavalid;
1284  s7_readdata <= m7_readdata;
1285 
1286  m8_burstcount <= s8_burstcount;
1287  m8_writedata <= s8_writedata;
1288  m8_address <= s8_address;
1289  m8_write <= s8_write;
1290  m8_read <= s8_read when i_frozzen(8) = '0' else '0';
1291  m8_byteenable <= s8_byteenable;
1292  m8_debugaccess <= s8_debugaccess;
1293  s8_waitrequest <= m8_waitrequest when i_frozzen(8) = '0' else '1';
1294  s8_readdatavalid <= m8_readdatavalid;
1295  s8_readdata <= m8_readdata;
1296 
1297  m9_burstcount <= s9_burstcount;
1298  m9_writedata <= s9_writedata;
1299  m9_address <= s9_address;
1300  m9_write <= s9_write;
1301  m9_read <= s9_read when i_frozzen(9) = '0' else '0';
1302  m9_byteenable <= s9_byteenable;
1303  m9_debugaccess <= s9_debugaccess;
1304  s9_waitrequest <= m9_waitrequest when i_frozzen(9) = '0' else '1';
1305  s9_readdatavalid <= m9_readdatavalid;
1306  s9_readdata <= m9_readdata;
1307 
1308  m10_burstcount <= s10_burstcount;
1309  m10_writedata <= s10_writedata;
1310  m10_address <= s10_address;
1311  m10_write <= s10_write;
1312  m10_read <= s10_read when i_frozzen(10) = '0' else '0';
1313  m10_byteenable <= s10_byteenable;
1314  m10_debugaccess <= s10_debugaccess;
1315  s10_waitrequest <= m10_waitrequest when i_frozzen(10) = '0' else '1';
1316  s10_readdatavalid <= m10_readdatavalid;
1317  s10_readdata <= m10_readdata;
1318 
1319  m11_burstcount <= s11_burstcount;
1320  m11_writedata <= s11_writedata;
1321  m11_address <= s11_address;
1322  m11_write <= s11_write;
1323  m11_read <= s11_read when i_frozzen(11) = '0' else '0';
1324  m11_byteenable <= s11_byteenable;
1325  m11_debugaccess <= s11_debugaccess;
1326  s11_waitrequest <= m11_waitrequest when i_frozzen(11) = '0' else '1';
1327  s11_readdatavalid <= m11_readdatavalid;
1328  s11_readdata <= m11_readdata;
1329 
1330  m12_burstcount <= s12_burstcount;
1331  m12_writedata <= s12_writedata;
1332  m12_address <= s12_address;
1333  m12_write <= s12_write;
1334  m12_read <= s12_read when i_frozzen(12) = '0' else '0';
1335  m12_byteenable <= s12_byteenable;
1336  m12_debugaccess <= s12_debugaccess;
1337  s12_waitrequest <= m12_waitrequest when i_frozzen(12) = '0' else '1';
1338  s12_readdatavalid <= m12_readdatavalid;
1339  s12_readdata <= m12_readdata;
1340 
1341  m13_burstcount <= s13_burstcount;
1342  m13_writedata <= s13_writedata;
1343  m13_address <= s13_address;
1344  m13_write <= s13_write;
1345  m13_read <= s13_read when i_frozzen(13) = '0' else '0';
1346  m13_byteenable <= s13_byteenable;
1347  m13_debugaccess <= s13_debugaccess;
1348  s13_waitrequest <= m13_waitrequest when i_frozzen(13) = '0' else '1';
1349  s13_readdatavalid <= m13_readdatavalid;
1350  s13_readdata <= m13_readdata;
1351 
1352  m14_burstcount <= s14_burstcount;
1353  m14_writedata <= s14_writedata;
1354  m14_address <= s14_address;
1355  m14_write <= s14_write;
1356  m14_read <= s14_read when i_frozzen(14) = '0' else '0';
1357  m14_byteenable <= s14_byteenable;
1358  m14_debugaccess <= s14_debugaccess;
1359  s14_waitrequest <= m14_waitrequest when i_frozzen(14) = '0' else '1';
1360  s14_readdatavalid <= m14_readdatavalid;
1361  s14_readdata <= m14_readdata;
1362 
1363  m15_burstcount <= s15_burstcount;
1364  m15_writedata <= s15_writedata;
1365  m15_address <= s15_address;
1366  m15_write <= s15_write;
1367  m15_read <= s15_read when i_frozzen(15) = '0' else '0';
1368  m15_byteenable <= s15_byteenable;
1369  m15_debugaccess <= s15_debugaccess;
1370  s15_waitrequest <= m15_waitrequest when i_frozzen(15) = '0' else '1';
1371  s15_readdatavalid <= m15_readdatavalid;
1372  s15_readdata <= m15_readdata;
1373 
1374  m16_burstcount <= s16_burstcount;
1375  m16_writedata <= s16_writedata;
1376  m16_address <= s16_address;
1377  m16_write <= s16_write;
1378  m16_read <= s16_read when i_frozzen(16) = '0' else '0';
1379  m16_byteenable <= s16_byteenable;
1380  m16_debugaccess <= s16_debugaccess;
1381  s16_waitrequest <= m16_waitrequest when i_frozzen(16) = '0' else '1';
1382  s16_readdatavalid <= m16_readdatavalid;
1383  s16_readdata <= m16_readdata;
1384 
1385  m17_burstcount <= s17_burstcount;
1386  m17_writedata <= s17_writedata;
1387  m17_address <= s17_address;
1388  m17_write <= s17_write;
1389  m17_read <= s17_read when i_frozzen(17) = '0' else '0';
1390  m17_byteenable <= s17_byteenable;
1391  m17_debugaccess <= s17_debugaccess;
1392  s17_waitrequest <= m17_waitrequest when i_frozzen(17) = '0' else '1';
1393  s17_readdatavalid <= m17_readdatavalid;
1394  s17_readdata <= m17_readdata;
1395 
1396  m18_burstcount <= s18_burstcount;
1397  m18_writedata <= s18_writedata;
1398  m18_address <= s18_address;
1399  m18_write <= s18_write;
1400  m18_read <= s18_read when i_frozzen(18) = '0' else '0';
1401  m18_byteenable <= s18_byteenable;
1402  m18_debugaccess <= s18_debugaccess;
1403  s18_waitrequest <= m18_waitrequest when i_frozzen(18) = '0' else '1';
1404  s18_readdatavalid <= m18_readdatavalid;
1405  s18_readdata <= m18_readdata;
1406 
1407  m19_burstcount <= s19_burstcount;
1408  m19_writedata <= s19_writedata;
1409  m19_address <= s19_address;
1410  m19_write <= s19_write;
1411  m19_read <= s19_read when i_frozzen(19) = '0' else '0';
1412  m19_byteenable <= s19_byteenable;
1413  m19_debugaccess <= s19_debugaccess;
1414  s19_waitrequest <= m19_waitrequest when i_frozzen(19) = '0' else '1';
1415  s19_readdatavalid <= m19_readdatavalid;
1416  s19_readdata <= m19_readdata;
1417 
1418  m20_burstcount <= s20_burstcount;
1419  m20_writedata <= s20_writedata;
1420  m20_address <= s20_address;
1421  m20_write <= s20_write;
1422  m20_read <= s20_read when i_frozzen(20) = '0' else '0';
1423  m20_byteenable <= s20_byteenable;
1424  m20_debugaccess <= s20_debugaccess;
1425  s20_waitrequest <= m20_waitrequest when i_frozzen(20) = '0' else '1';
1426  s20_readdatavalid <= m20_readdatavalid;
1427  s20_readdata <= m20_readdata;
1428 
1429  m21_burstcount <= s21_burstcount;
1430  m21_writedata <= s21_writedata;
1431  m21_address <= s21_address;
1432  m21_write <= s21_write;
1433  m21_read <= s21_read when i_frozzen(21) = '0' else '0';
1434  m21_byteenable <= s21_byteenable;
1435  m21_debugaccess <= s21_debugaccess;
1436  s21_waitrequest <= m21_waitrequest when i_frozzen(21) = '0' else '1';
1437  s21_readdatavalid <= m21_readdatavalid;
1438  s21_readdata <= m21_readdata;
1439 
1440  m22_burstcount <= s22_burstcount;
1441  m22_writedata <= s22_writedata;
1442  m22_address <= s22_address;
1443  m22_write <= s22_write;
1444  m22_read <= s22_read when i_frozzen(22) = '0' else '0';
1445  m22_byteenable <= s22_byteenable;
1446  m22_debugaccess <= s22_debugaccess;
1447  s22_waitrequest <= m22_waitrequest when i_frozzen(22) = '0' else '1';
1448  s22_readdatavalid <= m22_readdatavalid;
1449  s22_readdata <= m22_readdata;
1450 
1451  m23_burstcount <= s23_burstcount;
1452  m23_writedata <= s23_writedata;
1453  m23_address <= s23_address;
1454  m23_write <= s23_write;
1455  m23_read <= s23_read when i_frozzen(23) = '0' else '0';
1456  m23_byteenable <= s23_byteenable;
1457  m23_debugaccess <= s23_debugaccess;
1458  s23_waitrequest <= m23_waitrequest when i_frozzen(23) = '0' else '1';
1459  s23_readdatavalid <= m23_readdatavalid;
1460  s23_readdata <= m23_readdata;
1461 
1462  m24_burstcount <= s24_burstcount;
1463  m24_writedata <= s24_writedata;
1464  m24_address <= s24_address;
1465  m24_write <= s24_write;
1466  m24_read <= s24_read when i_frozzen(24) = '0' else '0';
1467  m24_byteenable <= s24_byteenable;
1468  m24_debugaccess <= s24_debugaccess;
1469  s24_waitrequest <= m24_waitrequest when i_frozzen(24) = '0' else '1';
1470  s24_readdatavalid <= m24_readdatavalid;
1471  s24_readdata <= m24_readdata;
1472 
1473  m25_burstcount <= s25_burstcount;
1474  m25_writedata <= s25_writedata;
1475  m25_address <= s25_address;
1476  m25_write <= s25_write;
1477  m25_read <= s25_read when i_frozzen(25) = '0' else '0';
1478  m25_byteenable <= s25_byteenable;
1479  m25_debugaccess <= s25_debugaccess;
1480  s25_waitrequest <= m25_waitrequest when i_frozzen(25) = '0' else '1';
1481  s25_readdatavalid <= m25_readdatavalid;
1482  s25_readdata <= m25_readdata;
1483 
1484  m26_burstcount <= s26_burstcount;
1485  m26_writedata <= s26_writedata;
1486  m26_address <= s26_address;
1487  m26_write <= s26_write;
1488  m26_read <= s26_read when i_frozzen(26) = '0' else '0';
1489  m26_byteenable <= s26_byteenable;
1490  m26_debugaccess <= s26_debugaccess;
1491  s26_waitrequest <= m26_waitrequest when i_frozzen(26) = '0' else '1';
1492  s26_readdatavalid <= m26_readdatavalid;
1493  s26_readdata <= m26_readdata;
1494 
1495  m27_burstcount <= s27_burstcount;
1496  m27_writedata <= s27_writedata;
1497  m27_address <= s27_address;
1498  m27_write <= s27_write;
1499  m27_read <= s27_read when i_frozzen(27) = '0' else '0';
1500  m27_byteenable <= s27_byteenable;
1501  m27_debugaccess <= s27_debugaccess;
1502  s27_waitrequest <= m27_waitrequest when i_frozzen(27) = '0' else '1';
1503  s27_readdatavalid <= m27_readdatavalid;
1504  s27_readdata <= m27_readdata;
1505 
1506  m28_burstcount <= s28_burstcount;
1507  m28_writedata <= s28_writedata;
1508  m28_address <= s28_address;
1509  m28_write <= s28_write;
1510  m28_read <= s28_read when i_frozzen(28) = '0' else '0';
1511  m28_byteenable <= s28_byteenable;
1512  m28_debugaccess <= s28_debugaccess;
1513  s28_waitrequest <= m28_waitrequest when i_frozzen(28) = '0' else '1';
1514  s28_readdatavalid <= m28_readdatavalid;
1515  s28_readdata <= m28_readdata;
1516 
1517  m29_burstcount <= s29_burstcount;
1518  m29_writedata <= s29_writedata;
1519  m29_address <= s29_address;
1520  m29_write <= s29_write;
1521  m29_read <= s29_read when i_frozzen(29) = '0' else '0';
1522  m29_byteenable <= s29_byteenable;
1523  m29_debugaccess <= s29_debugaccess;
1524  s29_waitrequest <= m29_waitrequest when i_frozzen(29) = '0' else '1';
1525  s29_readdatavalid <= m29_readdatavalid;
1526  s29_readdata <= m29_readdata;
1527 
1528  m30_burstcount <= s30_burstcount;
1529  m30_writedata <= s30_writedata;
1530  m30_address <= s30_address;
1531  m30_write <= s30_write;
1532  m30_read <= s30_read when i_frozzen(30) = '0' else '0';
1533  m30_byteenable <= s30_byteenable;
1534  m30_debugaccess <= s30_debugaccess;
1535  s30_waitrequest <= m30_waitrequest when i_frozzen(30) = '0' else '1';
1536  s30_readdatavalid <= m30_readdatavalid;
1537  s30_readdata <= m30_readdata;
1538 
1539  m31_burstcount <= s31_burstcount;
1540  m31_writedata <= s31_writedata;
1541  m31_address <= s31_address;
1542  m31_write <= s31_write;
1543  m31_read <= s31_read when i_frozzen(31) = '0' else '0';
1544  m31_byteenable <= s31_byteenable;
1545  m31_debugaccess <= s31_debugaccess;
1546  s31_waitrequest <= m31_waitrequest when i_frozzen(31) = '0' else '1';
1547  s31_readdatavalid <= m31_readdatavalid;
1548  s31_readdata <= m31_readdata;
1549 
1550  m32_burstcount <= s32_burstcount;
1551  m32_writedata <= s32_writedata;
1552  m32_address <= s32_address;
1553  m32_write <= s32_write;
1554  m32_read <= s32_read when i_frozzen(32) = '0' else '0';
1555  m32_byteenable <= s32_byteenable;
1556  m32_debugaccess <= s32_debugaccess;
1557  s32_waitrequest <= m32_waitrequest when i_frozzen(32) = '0' else '1';
1558  s32_readdatavalid <= m32_readdatavalid;
1559  s32_readdata <= m32_readdata;
1560 
1561 
1562 end architecture AM1;
avalon_monitor.AM1.i22_read_fifo
STD_LOGIC i22_read_fifo
Definition: avalon_monitor.vhd:870
u25
STD_FIFO u25u25
Definition: avalon_monitor.vhd:957
avalon_monitor.m10_address
out m10_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:262
avalon_monitor.m25_address
out m25_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:592
avalon_monitor.s22_byteenable
in s22_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:519
avalon_monitor.AM1.i32_empty
STD_LOGIC i32_empty
Definition: avalon_monitor.vhd:880
avalon_monitor.AM1.i18_almost_full
STD_LOGIC i18_almost_full
Definition: avalon_monitor.vhd:866
avalon_monitor.slave_AvalonMonitor_writedata
in slave_AvalonMonitor_writedatastd_logic_vector( 31 downto 0)
Definition: avalon_monitor.vhd:43
avalon_monitor.AM1.i8_fifo_store
STD_LOGIC i8_fifo_store
Definition: avalon_monitor.vhd:856
avalon_monitor.m5_readdatavalid
in m5_readdatavalidstd_logic
Definition: avalon_monitor.vhd:149
avalon_monitor.AM1.i15_full
STD_LOGIC i15_full
Definition: avalon_monitor.vhd:863
u17
STD_FIFO u17u17
Definition: avalon_monitor.vhd:949
avalon_monitor.s11_byteenable
in s11_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:277
avalon_monitor.m21_debugaccess
out m21_debugaccessstd_logic
Definition: avalon_monitor.vhd:508
avalon_monitor.m5_burstcount
out m5_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:150
avalon_monitor.s14_burstcount
in s14_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:338
avalon_monitor.AM1.i19_read_fifo
STD_LOGIC i19_read_fifo
Definition: avalon_monitor.vhd:867
avalon_monitor.m15_write
out m15_writestd_logic
Definition: avalon_monitor.vhd:373
avalon_monitor.s11_write
in s11_writestd_logic
Definition: avalon_monitor.vhd:275
avalon_monitor.m26_read
out m26_readstd_logic
Definition: avalon_monitor.vhd:616
avalon_monitor.m18_byteenable
out m18_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:441
avalon_monitor.m13_write
out m13_writestd_logic
Definition: avalon_monitor.vhd:329
avalon_monitor.m17_readdata
in m17_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:412
avalon_monitor.AM1.i29_full
STD_LOGIC i29_full
Definition: avalon_monitor.vhd:877
avalon_monitor.AM1.ADDR_FIFO_28
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 28, slave_AvalonMonitor_address'length) ) ADDR_FIFO_28
Definition: avalon_monitor.vhd:805
avalon_monitor.m3_burstcount
out m3_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:106
avalon_monitor.m4_read
out m4_readstd_logic
Definition: avalon_monitor.vhd:132
avalon_monitor.s25_address
in s25_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:582
avalon_monitor.AM1.i7_full
STD_LOGIC i7_full
Definition: avalon_monitor.vhd:855
avalon_monitor.m23_waitrequest
in m23_waitrequeststd_logic
Definition: avalon_monitor.vhd:543
avalon_monitor.m13_waitrequest
in m13_waitrequeststd_logic
Definition: avalon_monitor.vhd:323
avalon_monitor.s32_debugaccess
in s32_debugaccessstd_logic
Definition: avalon_monitor.vhd:740
avalon_monitor.s11_burstcount
in s11_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:272
avalon_monitor.s17_read
in s17_readstd_logic
Definition: avalon_monitor.vhd:408
avalon_monitor.m1_byteenable
out m1_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:67
avalon_monitor.s32_read
in s32_readstd_logic
Definition: avalon_monitor.vhd:738
u5
STD_FIFO u5u5
Definition: avalon_monitor.vhd:937
avalon_monitor.s3_byteenable
in s3_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:101
avalon_monitor.AVALON_DATA_FIFO_DEPTH
AVALON_DATA_FIFO_DEPTHinteger := 8
Definition: avalon_monitor.vhd:26
avalon_monitor.m29_writedata
out m29_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:679
avalon_monitor.m22_writedata
out m22_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:525
avalon_monitor.s30_debugaccess
in s30_debugaccessstd_logic
Definition: avalon_monitor.vhd:696
avalon_monitor.DATA_WIDTH
DATA_WIDTHinteger := 32
Definition: avalon_monitor.vhd:21
avalon_monitor.AM1.ADDR_FIFO_14
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 14, slave_AvalonMonitor_address'length) ) ADDR_FIFO_14
Definition: avalon_monitor.vhd:791
avalon_monitor.s27_waitrequest
out s27_waitrequeststd_logic
Definition: avalon_monitor.vhd:621
avalon_monitor.m12_waitrequest
in m12_waitrequeststd_logic
Definition: avalon_monitor.vhd:301
avalon_monitor.AM1.i15_empty
STD_LOGIC i15_empty
Definition: avalon_monitor.vhd:863
STD_FIFO.FIFO_DEPTH
FIFO_DEPTHpositive := 256
Definition: STD_FIFO.vhd:9
avalon_monitor.AM1.i6_empty
STD_LOGIC i6_empty
Definition: avalon_monitor.vhd:854
STD_FIFO
Definition: STD_FIFO.vhd:5
avalon_monitor.s32_burstcount
in s32_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:734
avalon_monitor.AM1.i13_fifo_store
STD_LOGIC i13_fifo_store
Definition: avalon_monitor.vhd:861
avalon_monitor.s9_burstcount
in s9_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:228
avalon_monitor.AM1.i13_almost_full
STD_LOGIC i13_almost_full
Definition: avalon_monitor.vhd:861
avalon_monitor.s11_waitrequest
out s11_waitrequeststd_logic
Definition: avalon_monitor.vhd:269
avalon_monitor.m13_byteenable
out m13_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:331
avalon_monitor.m12_read
out m12_readstd_logic
Definition: avalon_monitor.vhd:308
avalon_monitor.slave_AvalonMonitor_readdata
out slave_AvalonMonitor_readdatastd_logic_vector( 31 downto 0)
Definition: avalon_monitor.vhd:42
avalon_monitor.s28_address
in s28_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:648
u24
STD_FIFO u24u24
Definition: avalon_monitor.vhd:956
avalon_monitor.s1_byteenable
in s1_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:57
avalon_monitor.m17_readdatavalid
in m17_readdatavalidstd_logic
Definition: avalon_monitor.vhd:413
avalon_monitor.s26_writedata
in s26_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:603
avalon_monitor.s5_readdata
out s5_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:138
avalon_monitor.m31_write
out m31_writestd_logic
Definition: avalon_monitor.vhd:725
avalon_monitor.m22_debugaccess
out m22_debugaccessstd_logic
Definition: avalon_monitor.vhd:530
avalon_monitor.AM1.i18_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i18_data_out
Definition: avalon_monitor.vhd:829
avalon_monitor.AM1.ADDR_FIFO_12
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 12, slave_AvalonMonitor_address'length) ) ADDR_FIFO_12
Definition: avalon_monitor.vhd:789
avalon_monitor.AM1.i20_empty
STD_LOGIC i20_empty
Definition: avalon_monitor.vhd:868
avalon_monitor.s23_write
in s23_writestd_logic
Definition: avalon_monitor.vhd:539
avalon_monitor.m4_debugaccess
out m4_debugaccessstd_logic
Definition: avalon_monitor.vhd:134
avalon_monitor.m12_byteenable
out m12_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:309
avalon_monitor.m24_readdata
in m24_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:566
avalon_monitor.s27_write
in s27_writestd_logic
Definition: avalon_monitor.vhd:627
avalon_monitor.s2_waitrequest
out s2_waitrequeststd_logic
Definition: avalon_monitor.vhd:71
avalon_monitor.s24_readdatavalid
out s24_readdatavalidstd_logic
Definition: avalon_monitor.vhd:557
avalon_monitor.s13_address
in s13_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:318
u6
STD_FIFO u6u6
Definition: avalon_monitor.vhd:938
avalon_monitor.s4_byteenable
in s4_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:123
avalon_monitor.s30_burstcount
in s30_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:690
avalon_monitor.m18_address
out m18_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:438
avalon_monitor.s10_burstcount
in s10_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:250
avalon_monitor.AM1.i9_full
STD_LOGIC i9_full
Definition: avalon_monitor.vhd:857
avalon_monitor.s29_debugaccess
in s29_debugaccessstd_logic
Definition: avalon_monitor.vhd:674
avalon_monitor.AM1.i21_read_fifo
STD_LOGIC i21_read_fifo
Definition: avalon_monitor.vhd:869
avalon_monitor.s26_burstcount
in s26_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:602
avalon_monitor.s4_burstcount
in s4_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:118
avalon_monitor.m29_byteenable
out m29_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:683
avalon_monitor.m22_byteenable
out m22_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:529
avalon_monitor.m30_readdatavalid
in m30_readdatavalidstd_logic
Definition: avalon_monitor.vhd:699
avalon_monitor.s17_writedata
in s17_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:405
avalon_monitor.s26_read
in s26_readstd_logic
Definition: avalon_monitor.vhd:606
avalon_monitor.m6_burstcount
out m6_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:172
avalon_monitor.s18_debugaccess
in s18_debugaccessstd_logic
Definition: avalon_monitor.vhd:432
avalon_monitor.m24_address
out m24_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:570
avalon_monitor.s13_readdata
out s13_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:314
avalon_monitor.s28_byteenable
in s28_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:651
avalon_monitor.m25_readdata
in m25_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:588
avalon_monitor.m10_readdata
in m10_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:258
avalon_monitor.s17_readdatavalid
out s17_readdatavalidstd_logic
Definition: avalon_monitor.vhd:403
avalon_monitor.s22_burstcount
in s22_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:514
avalon_monitor.s13_byteenable
in s13_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:321
avalon_monitor.AM1.ADDR_FIFO_25
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 25, slave_AvalonMonitor_address'length) ) ADDR_FIFO_25
Definition: avalon_monitor.vhd:802
avalon_monitor.m19_readdatavalid
in m19_readdatavalidstd_logic
Definition: avalon_monitor.vhd:457
avalon_monitor.AM1.i26_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i26_data_out
Definition: avalon_monitor.vhd:837
avalon_monitor.s5_writedata
in s5_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:141
avalon_monitor.NProcessors
NProcessorsinteger
Definition: avalon_monitor.vhd:20
avalon_monitor.AM1.i27_empty
STD_LOGIC i27_empty
Definition: avalon_monitor.vhd:875
avalon_monitor.s23_waitrequest
out s23_waitrequeststd_logic
Definition: avalon_monitor.vhd:533
avalon_monitor.m31_writedata
out m31_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:723
avalon_monitor.s29_readdatavalid
out s29_readdatavalidstd_logic
Definition: avalon_monitor.vhd:667
avalon_monitor.m17_read
out m17_readstd_logic
Definition: avalon_monitor.vhd:418
avalon_monitor.m7_write
out m7_writestd_logic
Definition: avalon_monitor.vhd:197
avalon_monitor.s1_burstcount
in s1_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:52
avalon_monitor.AM1.i7_almost_full
STD_LOGIC i7_almost_full
Definition: avalon_monitor.vhd:855
avalon_monitor.s18_address
in s18_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:428
avalon_monitor.s30_waitrequest
out s30_waitrequeststd_logic
Definition: avalon_monitor.vhd:687
avalon_monitor.AM1.i20_fifo_store
STD_LOGIC i20_fifo_store
Definition: avalon_monitor.vhd:868
u27
STD_FIFO u27u27
Definition: avalon_monitor.vhd:959
avalon_monitor.s17_byteenable
in s17_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:409
STD_FIFO.WriteEn
in WriteEnSTD_LOGIC
Definition: STD_FIFO.vhd:13
avalon_monitor.m2_burstcount
out m2_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:84
avalon_monitor.m26_write
out m26_writestd_logic
Definition: avalon_monitor.vhd:615
avalon_monitor.AM1.i19_almost_full
STD_LOGIC i19_almost_full
Definition: avalon_monitor.vhd:867
u8
STD_FIFO u8u8
Definition: avalon_monitor.vhd:940
avalon_monitor.AM1.i12_empty
STD_LOGIC i12_empty
Definition: avalon_monitor.vhd:860
avalon_monitor.AM1.R_CTRL
STD_LOGIC_VECTOR( 31 downto 0) R_CTRL
Definition: avalon_monitor.vhd:891
avalon_monitor.s12_byteenable
in s12_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:299
avalon_monitor.m18_writedata
out m18_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:437
avalon_monitor.s10_byteenable
in s10_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:255
avalon_monitor.s12_write
in s12_writestd_logic
Definition: avalon_monitor.vhd:297
avalon_monitor.s20_readdata
out s20_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:468
avalon_monitor.m2_debugaccess
out m2_debugaccessstd_logic
Definition: avalon_monitor.vhd:90
avalon_monitor.s8_writedata
in s8_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:207
avalon_monitor.m22_write
out m22_writestd_logic
Definition: avalon_monitor.vhd:527
avalon_monitor.m25_burstcount
out m25_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:590
avalon_monitor.AM1.i2_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i2_address_prev
Definition: avalon_monitor.vhd:813
avalon_monitor.m14_waitrequest
in m14_waitrequeststd_logic
Definition: avalon_monitor.vhd:345
avalon_monitor.s7_readdatavalid
out s7_readdatavalidstd_logic
Definition: avalon_monitor.vhd:183
avalon_monitor.m18_read
out m18_readstd_logic
Definition: avalon_monitor.vhd:440
avalon_monitor.s4_readdatavalid
out s4_readdatavalidstd_logic
Definition: avalon_monitor.vhd:117
avalon_monitor.AM1.i11_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i11_data_out
Definition: avalon_monitor.vhd:822
avalon_monitor.m11_address
out m11_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:284
avalon_monitor.s3_burstcount
in s3_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:96
avalon_monitor.s14_readdatavalid
out s14_readdatavalidstd_logic
Definition: avalon_monitor.vhd:337
avalon_monitor.s14_readdata
out s14_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:336
avalon_monitor.m11_read
out m11_readstd_logic
Definition: avalon_monitor.vhd:286
avalon_monitor.AM1.i11_read_fifo
STD_LOGIC i11_read_fifo
Definition: avalon_monitor.vhd:859
avalon_monitor.m1_address
out m1_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:64
avalon_monitor.s19_write
in s19_writestd_logic
Definition: avalon_monitor.vhd:451
avalon_monitor.AM1.i9_fifo_store
STD_LOGIC i9_fifo_store
Definition: avalon_monitor.vhd:857
avalon_monitor.AM1.ADDR_FIFO_4
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 4, slave_AvalonMonitor_address'length) ) ADDR_FIFO_4
Definition: avalon_monitor.vhd:781
avalon_monitor.m31_read
out m31_readstd_logic
Definition: avalon_monitor.vhd:726
avalon_monitor.s31_address
in s31_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:714
avalon_monitor.AM1.i30_fifo_store
STD_LOGIC i30_fifo_store
Definition: avalon_monitor.vhd:878
avalon_monitor.m29_waitrequest
in m29_waitrequeststd_logic
Definition: avalon_monitor.vhd:675
avalon_monitor.s5_write
in s5_writestd_logic
Definition: avalon_monitor.vhd:143
avalon_monitor.AM1.i24_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i24_data_out
Definition: avalon_monitor.vhd:835
avalon_monitor.AM1.i29_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i29_address_prev
Definition: avalon_monitor.vhd:840
avalon_monitor.s20_burstcount
in s20_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:470
avalon_monitor.m1_write
out m1_writestd_logic
Definition: avalon_monitor.vhd:65
avalon_monitor.AM1.ADDR_FIFO_11
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 11, slave_AvalonMonitor_address'length) ) ADDR_FIFO_11
Definition: avalon_monitor.vhd:788
avalon_monitor.s19_burstcount
in s19_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:448
avalon_monitor.m20_readdata
in m20_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:478
avalon_monitor.s29_writedata
in s29_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:669
avalon_monitor.s16_write
in s16_writestd_logic
Definition: avalon_monitor.vhd:385
avalon_monitor.AM1.i19_full
STD_LOGIC i19_full
Definition: avalon_monitor.vhd:867
avalon_monitor.AM1.i17_almost_full
STD_LOGIC i17_almost_full
Definition: avalon_monitor.vhd:865
avalon_monitor.s7_writedata
in s7_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:185
u19
STD_FIFO u19u19
Definition: avalon_monitor.vhd:951
avalon_monitor.m25_writedata
out m25_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:591
avalon_monitor.AM1.i32_full
STD_LOGIC i32_full
Definition: avalon_monitor.vhd:880
avalon_monitor.AM1.i12_full
STD_LOGIC i12_full
Definition: avalon_monitor.vhd:860
avalon_monitor.s30_byteenable
in s30_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:695
avalon_monitor.AM1.i25_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i25_address_prev
Definition: avalon_monitor.vhd:836
avalon_monitor.s1_writedata
in s1_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:53
avalon_monitor.m20_debugaccess
out m20_debugaccessstd_logic
Definition: avalon_monitor.vhd:486
avalon_monitor.m9_burstcount
out m9_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:238
avalon_monitor.AM1.i10_almost_full
STD_LOGIC i10_almost_full
Definition: avalon_monitor.vhd:858
avalon_monitor.m8_burstcount
out m8_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:216
avalon_monitor.AM1.i14_fifo_store
STD_LOGIC i14_fifo_store
Definition: avalon_monitor.vhd:862
avalon_monitor.clk
in clkstd_logic
Definition: avalon_monitor.vhd:31
avalon_monitor.s8_address
in s8_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:208
avalon_monitor.m31_readdatavalid
in m31_readdatavalidstd_logic
Definition: avalon_monitor.vhd:721
avalon_monitor.m10_burstcount
out m10_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:260
avalon_monitor.s13_writedata
in s13_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:317
avalon_monitor.AM1.i11_full
STD_LOGIC i11_full
Definition: avalon_monitor.vhd:859
avalon_monitor.m28_read
out m28_readstd_logic
Definition: avalon_monitor.vhd:660
avalon_monitor.s25_read
in s25_readstd_logic
Definition: avalon_monitor.vhd:584
avalon_monitor.AM1.i30_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i30_data_out
Definition: avalon_monitor.vhd:841
avalon_monitor.s13_readdatavalid
out s13_readdatavalidstd_logic
Definition: avalon_monitor.vhd:315
avalon_monitor.s3_readdatavalid
out s3_readdatavalidstd_logic
Definition: avalon_monitor.vhd:95
avalon_monitor.s31_readdata
out s31_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:710
avalon_monitor.AM1.i22_empty
STD_LOGIC i22_empty
Definition: avalon_monitor.vhd:870
avalon_monitor.m24_readdatavalid
in m24_readdatavalidstd_logic
Definition: avalon_monitor.vhd:567
STD_FIFO.RST
in RSTSTD_LOGIC
Definition: STD_FIFO.vhd:12
avalon_monitor.s21_write
in s21_writestd_logic
Definition: avalon_monitor.vhd:495
avalon_monitor.m2_address
out m2_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:86
avalon_monitor.m7_address
out m7_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:196
avalon_monitor.s10_writedata
in s10_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:251
avalon_monitor.m32_writedata
out m32_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:745
avalon_monitor.m4_byteenable
out m4_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:133
avalon_monitor.m16_debugaccess
out m16_debugaccessstd_logic
Definition: avalon_monitor.vhd:398
avalon_monitor.s22_write
in s22_writestd_logic
Definition: avalon_monitor.vhd:517
avalon_monitor
Definition: avalon_monitor.vhd:16
avalon_monitor.s19_waitrequest
out s19_waitrequeststd_logic
Definition: avalon_monitor.vhd:445
avalon_monitor.s22_address
in s22_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:516
avalon_monitor.AM1.i31_fifo_store
STD_LOGIC i31_fifo_store
Definition: avalon_monitor.vhd:879
avalon_monitor.s21_debugaccess
in s21_debugaccessstd_logic
Definition: avalon_monitor.vhd:498
u16
STD_FIFO u16u16
Definition: avalon_monitor.vhd:948
avalon_monitor.s28_readdata
out s28_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:644
avalon_monitor.AM1.i12_almost_full
STD_LOGIC i12_almost_full
Definition: avalon_monitor.vhd:860
avalon_monitor.s6_readdatavalid
out s6_readdatavalidstd_logic
Definition: avalon_monitor.vhd:161
avalon_monitor.AM1.i4_full
STD_LOGIC i4_full
Definition: avalon_monitor.vhd:852
avalon_monitor.m21_read
out m21_readstd_logic
Definition: avalon_monitor.vhd:506
avalon_monitor.AM1.i9_almost_full
STD_LOGIC i9_almost_full
Definition: avalon_monitor.vhd:857
avalon_monitor.m9_writedata
out m9_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:239
avalon_monitor.s31_writedata
in s31_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:713
avalon_monitor.m30_address
out m30_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:702
avalon_monitor.AM1.i7_read_fifo
STD_LOGIC i7_read_fifo
Definition: avalon_monitor.vhd:855
avalon_monitor.s7_burstcount
in s7_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:184
avalon_monitor.s31_write
in s31_writestd_logic
Definition: avalon_monitor.vhd:715
avalon_monitor.m6_debugaccess
out m6_debugaccessstd_logic
Definition: avalon_monitor.vhd:178
avalon_monitor.AM1.i1_fifo_store
STD_LOGIC i1_fifo_store
Definition: avalon_monitor.vhd:849
avalon_monitor.s14_read
in s14_readstd_logic
Definition: avalon_monitor.vhd:342
avalon_monitor.m23_byteenable
out m23_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:551
avalon_monitor.AM1.i14_empty
STD_LOGIC i14_empty
Definition: avalon_monitor.vhd:862
avalon_monitor.m19_writedata
out m19_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:459
avalon_monitor.m5_address
out m5_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:152
avalon_monitor.m8_waitrequest
in m8_waitrequeststd_logic
Definition: avalon_monitor.vhd:213
avalon_monitor.s6_debugaccess
in s6_debugaccessstd_logic
Definition: avalon_monitor.vhd:168
avalon_monitor.m32_byteenable
out m32_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:749
avalon_monitor.m28_readdata
in m28_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:654
avalon_monitor.m19_debugaccess
out m19_debugaccessstd_logic
Definition: avalon_monitor.vhd:464
avalon_monitor.s16_readdata
out s16_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:380
avalon_monitor.AM1.i14_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i14_address_prev
Definition: avalon_monitor.vhd:825
avalon_monitor.AM1.i5_empty
STD_LOGIC i5_empty
Definition: avalon_monitor.vhd:853
avalon_monitor.m1_readdatavalid
in m1_readdatavalidstd_logic
Definition: avalon_monitor.vhd:61
avalon_monitor.s4_waitrequest
out s4_waitrequeststd_logic
Definition: avalon_monitor.vhd:115
avalon_monitor.m24_write
out m24_writestd_logic
Definition: avalon_monitor.vhd:571
avalon_monitor.m22_address
out m22_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:526
avalon_monitor.s20_readdatavalid
out s20_readdatavalidstd_logic
Definition: avalon_monitor.vhd:469
avalon_monitor.AM1.i17_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i17_data_out
Definition: avalon_monitor.vhd:828
avalon_monitor.AM1.ADDR_FIFO_26
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 26, slave_AvalonMonitor_address'length) ) ADDR_FIFO_26
Definition: avalon_monitor.vhd:803
avalon_monitor.AM1.i30_read_fifo
STD_LOGIC i30_read_fifo
Definition: avalon_monitor.vhd:878
avalon_monitor.m8_read
out m8_readstd_logic
Definition: avalon_monitor.vhd:220
avalon_monitor.m16_readdata
in m16_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:390
avalon_monitor.AM1.i2_almost_full
STD_LOGIC i2_almost_full
Definition: avalon_monitor.vhd:850
avalon_monitor.m26_burstcount
out m26_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:612
avalon_monitor.s13_debugaccess
in s13_debugaccessstd_logic
Definition: avalon_monitor.vhd:322
avalon_monitor.s11_address
in s11_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:274
avalon_monitor.AM1.ADDR_FIFO_30
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 30, slave_AvalonMonitor_address'length) ) ADDR_FIFO_30
Definition: avalon_monitor.vhd:807
avalon_monitor.AM1.i10_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i10_address_prev
Definition: avalon_monitor.vhd:821
avalon_monitor.m24_writedata
out m24_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:569
avalon_monitor.AM1.i19_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i19_address_prev
Definition: avalon_monitor.vhd:830
avalon_monitor.m21_byteenable
out m21_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:507
avalon_monitor.AM1.i26_fifo_store
STD_LOGIC i26_fifo_store
Definition: avalon_monitor.vhd:874
avalon_monitor.m24_read
out m24_readstd_logic
Definition: avalon_monitor.vhd:572
avalon_monitor.m16_write
out m16_writestd_logic
Definition: avalon_monitor.vhd:395
avalon_monitor.AM1.i2_fifo_store
STD_LOGIC i2_fifo_store
Definition: avalon_monitor.vhd:850
avalon_monitor.AM1.i26_full
STD_LOGIC i26_full
Definition: avalon_monitor.vhd:874
avalon_monitor.s29_waitrequest
out s29_waitrequeststd_logic
Definition: avalon_monitor.vhd:665
avalon_monitor.s22_readdatavalid
out s22_readdatavalidstd_logic
Definition: avalon_monitor.vhd:513
avalon_monitor.AM1.i17_full
STD_LOGIC i17_full
Definition: avalon_monitor.vhd:865
avalon_monitor.s11_read
in s11_readstd_logic
Definition: avalon_monitor.vhd:276
avalon_monitor.AM1.i4_empty
STD_LOGIC i4_empty
Definition: avalon_monitor.vhd:852
avalon_monitor.AM1.ADDR_FIFO_1
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 1, slave_AvalonMonitor_address'length) ) ADDR_FIFO_1
Definition: avalon_monitor.vhd:778
avalon_monitor.AM1.ADDR_FIFO_27
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 27, slave_AvalonMonitor_address'length) ) ADDR_FIFO_27
Definition: avalon_monitor.vhd:804
avalon_monitor.AM1.i16_almost_full
STD_LOGIC i16_almost_full
Definition: avalon_monitor.vhd:864
avalon_monitor.m12_burstcount
out m12_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:304
avalon_monitor.m8_readdatavalid
in m8_readdatavalidstd_logic
Definition: avalon_monitor.vhd:215
avalon_monitor.m30_debugaccess
out m30_debugaccessstd_logic
Definition: avalon_monitor.vhd:706
avalon_monitor.m32_debugaccess
out m32_debugaccessstd_logic
Definition: avalon_monitor.vhd:752
avalon_monitor.m9_readdatavalid
in m9_readdatavalidstd_logic
Definition: avalon_monitor.vhd:237
avalon_monitor.AM1.i6_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i6_address_prev
Definition: avalon_monitor.vhd:817
avalon_monitor.AM1.i29_read_fifo
STD_LOGIC i29_read_fifo
Definition: avalon_monitor.vhd:877
avalon_monitor.s1_debugaccess
in s1_debugaccessstd_logic
Definition: avalon_monitor.vhd:58
avalon_monitor.s2_readdata
out s2_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:72
avalon_monitor.m30_waitrequest
in m30_waitrequeststd_logic
Definition: avalon_monitor.vhd:697
avalon_monitor.m8_write
out m8_writestd_logic
Definition: avalon_monitor.vhd:219
avalon_monitor.s4_readdata
out s4_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:116
avalon_monitor.m25_debugaccess
out m25_debugaccessstd_logic
Definition: avalon_monitor.vhd:596
avalon_monitor.s27_debugaccess
in s27_debugaccessstd_logic
Definition: avalon_monitor.vhd:630
avalon_monitor.m1_debugaccess
out m1_debugaccessstd_logic
Definition: avalon_monitor.vhd:68
avalon_monitor.AM1.ADDR_FIFO_20
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 20, slave_AvalonMonitor_address'length) ) ADDR_FIFO_20
Definition: avalon_monitor.vhd:797
avalon_monitor.m4_waitrequest
in m4_waitrequeststd_logic
Definition: avalon_monitor.vhd:125
avalon_monitor.m5_waitrequest
in m5_waitrequeststd_logic
Definition: avalon_monitor.vhd:147
avalon_monitor.AM1.i21_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i21_data_out
Definition: avalon_monitor.vhd:832
avalon_monitor.s7_read
in s7_readstd_logic
Definition: avalon_monitor.vhd:188
STD_FIFO.Empty
out EmptySTD_LOGIC
Definition: STD_FIFO.vhd:17
avalon_monitor.s23_address
in s23_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:538
avalon_monitor.m17_write
out m17_writestd_logic
Definition: avalon_monitor.vhd:417
u2
STD_FIFO u2u2
Definition: avalon_monitor.vhd:934
avalon_monitor.AM1.i28_empty
STD_LOGIC i28_empty
Definition: avalon_monitor.vhd:876
avalon_monitor.AM1.i27_fifo_store
STD_LOGIC i27_fifo_store
Definition: avalon_monitor.vhd:875
avalon_monitor.m28_waitrequest
in m28_waitrequeststd_logic
Definition: avalon_monitor.vhd:653
avalon_monitor.s26_readdatavalid
out s26_readdatavalidstd_logic
Definition: avalon_monitor.vhd:601
avalon_monitor.s31_debugaccess
in s31_debugaccessstd_logic
Definition: avalon_monitor.vhd:718
avalon_monitor.s8_read
in s8_readstd_logic
Definition: avalon_monitor.vhd:210
avalon_monitor.AM1.i6_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i6_data_out
Definition: avalon_monitor.vhd:817
avalon_monitor.slave_AvalonMonitor_chipselect
in slave_AvalonMonitor_chipselectstd_logic
Definition: avalon_monitor.vhd:38
avalon_monitor.s25_debugaccess
in s25_debugaccessstd_logic
Definition: avalon_monitor.vhd:586
STD_FIFO.DataIn
in DataInSTD_LOGIC_VECTOR( DATA_WIDTH- 1 downto 0)
Definition: STD_FIFO.vhd:14
avalon_monitor.m20_burstcount
out m20_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:480
avalon_monitor.m8_byteenable
out m8_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:221
avalon_bridge.ieee
_library_ ieeeieee
Definition: avalon_bridge.vhd:6
avalon_monitor.m21_writedata
out m21_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:503
avalon_monitor.s30_address
in s30_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:692
avalon_monitor.m24_burstcount
out m24_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:568
avalon_monitor.m11_writedata
out m11_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:283
avalon_monitor.s21_waitrequest
out s21_waitrequeststd_logic
Definition: avalon_monitor.vhd:489
avalon_monitor.m25_write
out m25_writestd_logic
Definition: avalon_monitor.vhd:593
avalon_monitor.m12_write
out m12_writestd_logic
Definition: avalon_monitor.vhd:307
avalon_monitor.AM1.i32_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i32_address_prev
Definition: avalon_monitor.vhd:843
avalon_monitor.s24_writedata
in s24_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:559
avalon_monitor.AM1.i1_read_fifo
STD_LOGIC i1_read_fifo
Definition: avalon_monitor.vhd:849
avalon_monitor.AM1.i15_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i15_address_prev
Definition: avalon_monitor.vhd:826
avalon_monitor.s18_read
in s18_readstd_logic
Definition: avalon_monitor.vhd:430
avalon_monitor.s13_waitrequest
out s13_waitrequeststd_logic
Definition: avalon_monitor.vhd:313
avalon_monitor.s21_byteenable
in s21_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:497
avalon_monitor.m17_writedata
out m17_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:415
avalon_monitor.m11_burstcount
out m11_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:282
avalon_monitor.s8_waitrequest
out s8_waitrequeststd_logic
Definition: avalon_monitor.vhd:203
avalon_monitor.m26_debugaccess
out m26_debugaccessstd_logic
Definition: avalon_monitor.vhd:618
avalon_monitor.m6_readdata
in m6_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:170
avalon_monitor.m31_byteenable
out m31_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:727
avalon_monitor.AM1.i28_almost_full
STD_LOGIC i28_almost_full
Definition: avalon_monitor.vhd:876
avalon_monitor.BURSTCOUNT_WIDTH
BURSTCOUNT_WIDTHinteger := 1
Definition: avalon_monitor.vhd:24
avalon_monitor.s19_byteenable
in s19_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:453
avalon_monitor.AM1.i30_full
STD_LOGIC i30_full
Definition: avalon_monitor.vhd:878
avalon_monitor.AM1.i21_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i21_address_prev
Definition: avalon_monitor.vhd:832
avalon_monitor.AM1.ADDR_FIFO_15
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 15, slave_AvalonMonitor_address'length) ) ADDR_FIFO_15
Definition: avalon_monitor.vhd:792
avalon_monitor.m23_debugaccess
out m23_debugaccessstd_logic
Definition: avalon_monitor.vhd:552
avalon_monitor.s6_read
in s6_readstd_logic
Definition: avalon_monitor.vhd:166
avalon_monitor.s8_burstcount
in s8_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:206
STD_FIFO.DATA_WIDTH
DATA_WIDTHpositive := 8
Definition: STD_FIFO.vhd:7
avalon_monitor.s23_writedata
in s23_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:537
avalon_monitor.s11_writedata
in s11_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:273
u29
STD_FIFO u29u29
Definition: avalon_monitor.vhd:961
avalon_monitor.s32_address
in s32_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:736
avalon_monitor.s13_read
in s13_readstd_logic
Definition: avalon_monitor.vhd:320
avalon_monitor.s24_address
in s24_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:560
avalon_monitor.m4_readdatavalid
in m4_readdatavalidstd_logic
Definition: avalon_monitor.vhd:127
avalon_monitor.m13_read
out m13_readstd_logic
Definition: avalon_monitor.vhd:330
avalon_monitor.AM1.i25_almost_full
STD_LOGIC i25_almost_full
Definition: avalon_monitor.vhd:873
avalon_monitor.m22_read
out m22_readstd_logic
Definition: avalon_monitor.vhd:528
avalon_monitor.AM1.i6_almost_full
STD_LOGIC i6_almost_full
Definition: avalon_monitor.vhd:854
avalon_monitor.m31_burstcount
out m31_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:722
avalon_monitor.s16_readdatavalid
out s16_readdatavalidstd_logic
Definition: avalon_monitor.vhd:381
avalon_monitor.AM1.i10_read_fifo
STD_LOGIC i10_read_fifo
Definition: avalon_monitor.vhd:858
avalon_monitor.m1_waitrequest
in m1_waitrequeststd_logic
Definition: avalon_monitor.vhd:59
STD_FIFO.Full
out FullSTD_LOGIC
Definition: STD_FIFO.vhd:20
avalon_monitor.AM1.i9_read_fifo
STD_LOGIC i9_read_fifo
Definition: avalon_monitor.vhd:857
avalon_monitor.AM1.ADDR_FIFO_19
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 19, slave_AvalonMonitor_address'length) ) ADDR_FIFO_19
Definition: avalon_monitor.vhd:796
avalon_monitor.s4_debugaccess
in s4_debugaccessstd_logic
Definition: avalon_monitor.vhd:124
avalon_monitor.m23_read
out m23_readstd_logic
Definition: avalon_monitor.vhd:550
avalon_monitor.s22_debugaccess
in s22_debugaccessstd_logic
Definition: avalon_monitor.vhd:520
avalon_monitor.m26_writedata
out m26_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:613
avalon_monitor.AM1.i18_full
STD_LOGIC i18_full
Definition: avalon_monitor.vhd:866
avalon_monitor.AM1.i5_fifo_store
STD_LOGIC i5_fifo_store
Definition: avalon_monitor.vhd:853
avalon_monitor.AM1.i32_almost_full
STD_LOGIC i32_almost_full
Definition: avalon_monitor.vhd:880
avalon_monitor.m2_readdatavalid
in m2_readdatavalidstd_logic
Definition: avalon_monitor.vhd:83
avalon_monitor.AM1.i22_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i22_data_out
Definition: avalon_monitor.vhd:833
avalon_monitor.m20_writedata
out m20_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:481
avalon_monitor.s7_debugaccess
in s7_debugaccessstd_logic
Definition: avalon_monitor.vhd:190
avalon_monitor.s18_readdata
out s18_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:424
avalon_monitor.AM1.ADDR_FIFO_8
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 8, slave_AvalonMonitor_address'length) ) ADDR_FIFO_8
Definition: avalon_monitor.vhd:785
avalon_monitor.s18_byteenable
in s18_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:431
avalon_monitor.m9_write
out m9_writestd_logic
Definition: avalon_monitor.vhd:241
avalon_monitor.m10_readdatavalid
in m10_readdatavalidstd_logic
Definition: avalon_monitor.vhd:259
avalon_monitor.m11_debugaccess
out m11_debugaccessstd_logic
Definition: avalon_monitor.vhd:288
avalon_monitor.s13_write
in s13_writestd_logic
Definition: avalon_monitor.vhd:319
avalon_monitor.slave_AvalonMonitor_read
in slave_AvalonMonitor_readstd_logic
Definition: avalon_monitor.vhd:40
avalon_monitor.AM1.i23_almost_full
STD_LOGIC i23_almost_full
Definition: avalon_monitor.vhd:871
avalon_monitor.frozen_avalon_monitor
out frozen_avalon_monitorstd_logic
Definition: avalon_monitor.vhd:35
avalon_monitor.m19_write
out m19_writestd_logic
Definition: avalon_monitor.vhd:461
avalon_monitor.AM1.i27_almost_full
STD_LOGIC i27_almost_full
Definition: avalon_monitor.vhd:875
avalon_monitor.s28_readdatavalid
out s28_readdatavalidstd_logic
Definition: avalon_monitor.vhd:645
avalon_monitor.m8_debugaccess
out m8_debugaccessstd_logic
Definition: avalon_monitor.vhd:222
u7
STD_FIFO u7u7
Definition: avalon_monitor.vhd:939
STD_FIFO.CLK
in CLKSTD_LOGIC
Definition: STD_FIFO.vhd:11
avalon_monitor.AM1.i4_almost_full
STD_LOGIC i4_almost_full
Definition: avalon_monitor.vhd:852
avalon_monitor.s15_write
in s15_writestd_logic
Definition: avalon_monitor.vhd:363
avalon_monitor.AM1.i21_empty
STD_LOGIC i21_empty
Definition: avalon_monitor.vhd:869
avalon_monitor.m32_burstcount
out m32_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:744
avalon_monitor.m6_waitrequest
in m6_waitrequeststd_logic
Definition: avalon_monitor.vhd:169
avalon_monitor.m32_waitrequest
in m32_waitrequeststd_logic
Definition: avalon_monitor.vhd:741
avalon_monitor.AM1.i18_fifo_store
STD_LOGIC i18_fifo_store
Definition: avalon_monitor.vhd:866
avalon_monitor.AM1.ADDR_FIFO_0
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 0, slave_AvalonMonitor_address'length) ) ADDR_FIFO_0
Definition: avalon_monitor.vhd:777
avalon_monitor.s18_writedata
in s18_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:427
avalon_monitor.AM1.i31_read_fifo
STD_LOGIC i31_read_fifo
Definition: avalon_monitor.vhd:879
avalon_monitor.m6_readdatavalid
in m6_readdatavalidstd_logic
Definition: avalon_monitor.vhd:171
avalon_monitor.s12_readdatavalid
out s12_readdatavalidstd_logic
Definition: avalon_monitor.vhd:293
avalon_monitor.AM1.i9_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i9_address_prev
Definition: avalon_monitor.vhd:820
avalon_monitor.AM1.i1_almost_full
STD_LOGIC i1_almost_full
Definition: avalon_monitor.vhd:849
avalon_monitor.m4_writedata
out m4_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:129
avalon_monitor.AM1.i8_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i8_data_out
Definition: avalon_monitor.vhd:819
avalon_monitor.s10_address
in s10_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:252
avalon_monitor.s25_writedata
in s25_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:581
avalon_monitor.AM1.i30_empty
STD_LOGIC i30_empty
Definition: avalon_monitor.vhd:878
avalon_monitor.m17_byteenable
out m17_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:419
avalon_monitor.m14_write
out m14_writestd_logic
Definition: avalon_monitor.vhd:351
avalon_monitor.m23_write
out m23_writestd_logic
Definition: avalon_monitor.vhd:549
avalon_monitor.s21_address
in s21_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:494
avalon_monitor.m11_byteenable
out m11_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:287
avalon_monitor.m5_read
out m5_readstd_logic
Definition: avalon_monitor.vhd:154
avalon_monitor.s19_read
in s19_readstd_logic
Definition: avalon_monitor.vhd:452
avalon_monitor.AM1.i22_fifo_store
STD_LOGIC i22_fifo_store
Definition: avalon_monitor.vhd:870
avalon_monitor.AM1.i18_read_fifo
STD_LOGIC i18_read_fifo
Definition: avalon_monitor.vhd:866
avalon_monitor.AM1.ADDR_FIFO_2
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 2, slave_AvalonMonitor_address'length) ) ADDR_FIFO_2
Definition: avalon_monitor.vhd:779
avalon_monitor.m13_writedata
out m13_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:327
avalon_monitor.s3_address
in s3_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:98
avalon_monitor.m20_address
out m20_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:482
avalon_monitor.s6_burstcount
in s6_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:162
u10
STD_FIFO u10u10
Definition: avalon_monitor.vhd:942
avalon_monitor.m12_debugaccess
out m12_debugaccessstd_logic
Definition: avalon_monitor.vhd:310
avalon_monitor.m27_byteenable
out m27_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:639
avalon_monitor.m23_burstcount
out m23_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:546
avalon_monitor.s24_read
in s24_readstd_logic
Definition: avalon_monitor.vhd:562
avalon_monitor.AM1.i26_almost_full
STD_LOGIC i26_almost_full
Definition: avalon_monitor.vhd:874
avalon_monitor.m21_write
out m21_writestd_logic
Definition: avalon_monitor.vhd:505
avalon_monitor.s8_readdatavalid
out s8_readdatavalidstd_logic
Definition: avalon_monitor.vhd:205
u30
STD_FIFO u30u30
Definition: avalon_monitor.vhd:962
avalon_monitor.m18_write
out m18_writestd_logic
Definition: avalon_monitor.vhd:439
avalon_monitor.AM1.i18_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i18_address_prev
Definition: avalon_monitor.vhd:829
avalon_monitor.AM1.i9_empty
STD_LOGIC i9_empty
Definition: avalon_monitor.vhd:857
avalon_monitor.AM1.i24_read_fifo
STD_LOGIC i24_read_fifo
Definition: avalon_monitor.vhd:872
avalon_monitor.s22_waitrequest
out s22_waitrequeststd_logic
Definition: avalon_monitor.vhd:511
avalon_monitor.m6_byteenable
out m6_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:177
avalon_monitor.m23_writedata
out m23_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:547
avalon_monitor.s24_burstcount
in s24_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:558
avalon_monitor.s27_writedata
in s27_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:625
avalon_monitor.AM1.i2_empty
STD_LOGIC i2_empty
Definition: avalon_monitor.vhd:850
avalon_monitor.m31_address
out m31_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:724
avalon_monitor.m23_address
out m23_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:548
avalon_monitor.AM1.i21_full
STD_LOGIC i21_full
Definition: avalon_monitor.vhd:869
avalon_monitor.AM1.i31_full
STD_LOGIC i31_full
Definition: avalon_monitor.vhd:879
avalon_monitor.AM1.i17_read_fifo
STD_LOGIC i17_read_fifo
Definition: avalon_monitor.vhd:865
avalon_monitor.s22_readdata
out s22_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:512
avalon_monitor.AM1.ADDR_FIFO_24
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 24, slave_AvalonMonitor_address'length) ) ADDR_FIFO_24
Definition: avalon_monitor.vhd:801
avalon_monitor.s12_readdata
out s12_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:292
avalon_monitor.AM1.i4_fifo_store
STD_LOGIC i4_fifo_store
Definition: avalon_monitor.vhd:852
avalon_monitor.s29_write
in s29_writestd_logic
Definition: avalon_monitor.vhd:671
avalon_monitor.m2_readdata
in m2_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:82
avalon_monitor.m9_read
out m9_readstd_logic
Definition: avalon_monitor.vhd:242
avalon_monitor.m25_waitrequest
in m25_waitrequeststd_logic
Definition: avalon_monitor.vhd:587
avalon_monitor.m3_readdatavalid
in m3_readdatavalidstd_logic
Definition: avalon_monitor.vhd:105
avalon_monitor.m27_write
out m27_writestd_logic
Definition: avalon_monitor.vhd:637
avalon_monitor.m10_debugaccess
out m10_debugaccessstd_logic
Definition: avalon_monitor.vhd:266
avalon_monitor.s21_readdatavalid
out s21_readdatavalidstd_logic
Definition: avalon_monitor.vhd:491
avalon_monitor.s20_debugaccess
in s20_debugaccessstd_logic
Definition: avalon_monitor.vhd:476
avalon_monitor.AM1.i11_empty
STD_LOGIC i11_empty
Definition: avalon_monitor.vhd:859
avalon_monitor.AM1.i31_empty
STD_LOGIC i31_empty
Definition: avalon_monitor.vhd:879
avalon_monitor.AM1.i3_read_fifo
STD_LOGIC i3_read_fifo
Definition: avalon_monitor.vhd:851
avalon_monitor.AM1.i4_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i4_address_prev
Definition: avalon_monitor.vhd:815
avalon_monitor.m4_burstcount
out m4_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:128
avalon_monitor.s3_write
in s3_writestd_logic
Definition: avalon_monitor.vhd:99
avalon_monitor.AM1.ADDR_FIFO_13
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 13, slave_AvalonMonitor_address'length) ) ADDR_FIFO_13
Definition: avalon_monitor.vhd:790
avalon_monitor.m10_writedata
out m10_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:261
avalon_monitor.reset
in resetstd_logic
Definition: avalon_monitor.vhd:32
avalon_monitor.AM1.i31_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i31_address_prev
Definition: avalon_monitor.vhd:842
avalon_monitor.AM1.i15_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i15_data_out
Definition: avalon_monitor.vhd:826
avalon_monitor.AM1.i24_fifo_store
STD_LOGIC i24_fifo_store
Definition: avalon_monitor.vhd:872
avalon_monitor.AM1.i16_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i16_data_out
Definition: avalon_monitor.vhd:827
avalon_monitor.s21_burstcount
in s21_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:492
avalon_monitor.s5_address
in s5_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:142
avalon_monitor.AM1.i13_read_fifo
STD_LOGIC i13_read_fifo
Definition: avalon_monitor.vhd:861
avalon_monitor.m15_debugaccess
out m15_debugaccessstd_logic
Definition: avalon_monitor.vhd:376
avalon_monitor.m24_waitrequest
in m24_waitrequeststd_logic
Definition: avalon_monitor.vhd:565
avalon_monitor.m27_debugaccess
out m27_debugaccessstd_logic
Definition: avalon_monitor.vhd:640
avalon_monitor.s32_writedata
in s32_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:735
avalon_monitor.m18_burstcount
out m18_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:436
avalon_monitor.s6_address
in s6_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:164
avalon_monitor.s20_read
in s20_readstd_logic
Definition: avalon_monitor.vhd:474
avalon_monitor.s1_readdatavalid
out s1_readdatavalidstd_logic
Definition: avalon_monitor.vhd:51
avalon_monitor.m15_readdatavalid
in m15_readdatavalidstd_logic
Definition: avalon_monitor.vhd:369
avalon_monitor.m4_readdata
in m4_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:126
avalon_monitor.s15_waitrequest
out s15_waitrequeststd_logic
Definition: avalon_monitor.vhd:357
avalon_monitor.m28_debugaccess
out m28_debugaccessstd_logic
Definition: avalon_monitor.vhd:662
avalon_monitor.m10_write
out m10_writestd_logic
Definition: avalon_monitor.vhd:263
avalon_monitor.AM1.ADDR_FIFO_23
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 23, slave_AvalonMonitor_address'length) ) ADDR_FIFO_23
Definition: avalon_monitor.vhd:800
avalon_monitor.AM1.i26_read_fifo
STD_LOGIC i26_read_fifo
Definition: avalon_monitor.vhd:874
avalon_monitor.s5_read
in s5_readstd_logic
Definition: avalon_monitor.vhd:144
avalon_monitor.m29_debugaccess
out m29_debugaccessstd_logic
Definition: avalon_monitor.vhd:684
avalon_monitor.s5_debugaccess
in s5_debugaccessstd_logic
Definition: avalon_monitor.vhd:146
u32
STD_FIFO u32u32
Definition: avalon_monitor.vhd:964
avalon_monitor.s32_write
in s32_writestd_logic
Definition: avalon_monitor.vhd:737
avalon_monitor.m1_readdata
in m1_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:60
avalon_monitor.m3_read
out m3_readstd_logic
Definition: avalon_monitor.vhd:110
avalon_monitor.s17_waitrequest
out s17_waitrequeststd_logic
Definition: avalon_monitor.vhd:401
avalon_monitor.m14_debugaccess
out m14_debugaccessstd_logic
Definition: avalon_monitor.vhd:354
avalon_monitor.s26_waitrequest
out s26_waitrequeststd_logic
Definition: avalon_monitor.vhd:599
u26
STD_FIFO u26u26
Definition: avalon_monitor.vhd:958
avalon_monitor.AM1.i30_almost_full
STD_LOGIC i30_almost_full
Definition: avalon_monitor.vhd:878
avalon_monitor.m32_address
out m32_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:746
avalon_monitor.AM1.i23_empty
STD_LOGIC i23_empty
Definition: avalon_monitor.vhd:871
avalon_monitor.m18_debugaccess
out m18_debugaccessstd_logic
Definition: avalon_monitor.vhd:442
avalon_monitor.m15_readdata
in m15_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:368
avalon_monitor.AM1.i22_almost_full
STD_LOGIC i22_almost_full
Definition: avalon_monitor.vhd:870
avalon_monitor.AM1.i16_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i16_address_prev
Definition: avalon_monitor.vhd:827
avalon_monitor.AM1.i28_full
STD_LOGIC i28_full
Definition: avalon_monitor.vhd:876
u20
STD_FIFO u20u20
Definition: avalon_monitor.vhd:952
avalon_monitor.s16_byteenable
in s16_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:387
avalon_monitor.AM1.i1_empty
STD_LOGIC i1_empty
Definition: avalon_monitor.vhd:849
avalon_monitor.AM1.i26_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i26_address_prev
Definition: avalon_monitor.vhd:837
avalon_monitor.AM1.i17_empty
STD_LOGIC i17_empty
Definition: avalon_monitor.vhd:865
avalon_monitor.AM1.i27_full
STD_LOGIC i27_full
Definition: avalon_monitor.vhd:875
avalon_monitor.m21_waitrequest
in m21_waitrequeststd_logic
Definition: avalon_monitor.vhd:499
avalon_monitor.AM1.i7_empty
STD_LOGIC i7_empty
Definition: avalon_monitor.vhd:855
avalon_monitor.m19_read
out m19_readstd_logic
Definition: avalon_monitor.vhd:462
avalon_monitor.m16_burstcount
out m16_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:392
avalon_monitor.m22_readdata
in m22_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:522
avalon_monitor.s25_byteenable
in s25_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:585
avalon_monitor.s5_byteenable
in s5_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:145
avalon_monitor.s17_burstcount
in s17_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:404
avalon_monitor.AM1.i24_full
STD_LOGIC i24_full
Definition: avalon_monitor.vhd:872
avalon_monitor.AM1.i19_empty
STD_LOGIC i19_empty
Definition: avalon_monitor.vhd:867
avalon_monitor.s19_address
in s19_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:450
avalon_monitor.AM1.i25_empty
STD_LOGIC i25_empty
Definition: avalon_monitor.vhd:873
avalon_monitor.m5_debugaccess
out m5_debugaccessstd_logic
Definition: avalon_monitor.vhd:156
avalon_monitor.s32_readdata
out s32_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:732
avalon_monitor.m16_readdatavalid
in m16_readdatavalidstd_logic
Definition: avalon_monitor.vhd:391
avalon_monitor.m11_readdata
in m11_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:280
avalon_monitor.m19_waitrequest
in m19_waitrequeststd_logic
Definition: avalon_monitor.vhd:455
avalon_monitor.s1_address
in s1_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:54
avalon_monitor.m16_read
out m16_readstd_logic
Definition: avalon_monitor.vhd:396
u12
STD_FIFO u12u12
Definition: avalon_monitor.vhd:944
avalon_monitor.m17_waitrequest
in m17_waitrequeststd_logic
Definition: avalon_monitor.vhd:411
avalon_monitor.AM1.i5_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i5_address_prev
Definition: avalon_monitor.vhd:816
avalon_monitor.m15_read
out m15_readstd_logic
Definition: avalon_monitor.vhd:374
avalon_monitor.AM1.i10_full
STD_LOGIC i10_full
Definition: avalon_monitor.vhd:858
avalon_monitor.AM1.i7_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i7_address_prev
Definition: avalon_monitor.vhd:818
avalon_monitor.m16_address
out m16_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:394
avalon_monitor.s22_writedata
in s22_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:515
STD_FIFO.DataOut
out DataOutSTD_LOGIC_VECTOR( DATA_WIDTH- 1 downto 0)
Definition: STD_FIFO.vhd:16
avalon_monitor.s7_readdata
out s7_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:182
avalon_monitor.AM1.i12_fifo_store
STD_LOGIC i12_fifo_store
Definition: avalon_monitor.vhd:860
avalon_monitor.m7_readdatavalid
in m7_readdatavalidstd_logic
Definition: avalon_monitor.vhd:193
u31
STD_FIFO u31u31
Definition: avalon_monitor.vhd:963
u15
STD_FIFO u15u15
Definition: avalon_monitor.vhd:947
avalon_monitor.s26_byteenable
in s26_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:607
avalon_monitor.AM1.i2_read_fifo
STD_LOGIC i2_read_fifo
Definition: avalon_monitor.vhd:850
avalon_monitor.m30_write
out m30_writestd_logic
Definition: avalon_monitor.vhd:703
avalon_monitor.m22_waitrequest
in m22_waitrequeststd_logic
Definition: avalon_monitor.vhd:521
avalon_monitor.s25_burstcount
in s25_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:580
avalon_monitor.s24_waitrequest
out s24_waitrequeststd_logic
Definition: avalon_monitor.vhd:555
avalon_monitor.AM1.i31_almost_full
STD_LOGIC i31_almost_full
Definition: avalon_monitor.vhd:879
avalon_monitor.AM1.i22_full
STD_LOGIC i22_full
Definition: avalon_monitor.vhd:870
avalon_monitor.AM1
Definition: avalon_monitor.vhd:756
avalon_monitor.m1_writedata
out m1_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:63
avalon_monitor.m20_readdatavalid
in m20_readdatavalidstd_logic
Definition: avalon_monitor.vhd:479
avalon_monitor.m28_write
out m28_writestd_logic
Definition: avalon_monitor.vhd:659
avalon_monitor.s26_debugaccess
in s26_debugaccessstd_logic
Definition: avalon_monitor.vhd:608
avalon_monitor.AM1.i20_almost_full
STD_LOGIC i20_almost_full
Definition: avalon_monitor.vhd:868
avalon_monitor.AM1.i3_fifo_store
STD_LOGIC i3_fifo_store
Definition: avalon_monitor.vhd:851
avalon_monitor.m7_byteenable
out m7_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:199
avalon_monitor.s7_waitrequest
out s7_waitrequeststd_logic
Definition: avalon_monitor.vhd:181
avalon_monitor.s10_waitrequest
out s10_waitrequeststd_logic
Definition: avalon_monitor.vhd:247
avalon_monitor.m27_address
out m27_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:636
avalon_monitor.m30_byteenable
out m30_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:705
avalon_monitor.s11_readdata
out s11_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:270
avalon_monitor.s29_byteenable
in s29_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:673
u18
STD_FIFO u18u18
Definition: avalon_monitor.vhd:950
avalon_monitor.m2_write
out m2_writestd_logic
Definition: avalon_monitor.vhd:87
avalon_monitor.s9_readdata
out s9_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:226
avalon_monitor.m29_write
out m29_writestd_logic
Definition: avalon_monitor.vhd:681
avalon_monitor.s28_debugaccess
in s28_debugaccessstd_logic
Definition: avalon_monitor.vhd:652
avalon_monitor.s16_debugaccess
in s16_debugaccessstd_logic
Definition: avalon_monitor.vhd:388
avalon_monitor.s16_address
in s16_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:384
avalon_monitor.DEVICE_FAMILY
DEVICE_FAMILYstring
Definition: avalon_monitor.vhd:28
avalon_monitor.AM1.i_frozzen
STD_LOGIC_VECTOR( 32 downto 1) i_frozzen
Definition: avalon_monitor.vhd:847
avalon_monitor.AM1.ADDR_FIFO_22
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 22, slave_AvalonMonitor_address'length) ) ADDR_FIFO_22
Definition: avalon_monitor.vhd:799
avalon_monitor.m16_byteenable
out m16_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:397
avalon_monitor.m5_byteenable
out m5_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:155
avalon_monitor.AM1.i12_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i12_data_out
Definition: avalon_monitor.vhd:823
avalon_monitor.m23_readdata
in m23_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:544
avalon_monitor.m3_byteenable
out m3_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:111
avalon_monitor.m10_read
out m10_readstd_logic
Definition: avalon_monitor.vhd:264
avalon_monitor.m29_readdatavalid
in m29_readdatavalidstd_logic
Definition: avalon_monitor.vhd:677
avalon_monitor.s3_read
in s3_readstd_logic
Definition: avalon_monitor.vhd:100
avalon_monitor.m15_burstcount
out m15_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:370
avalon_monitor.s14_waitrequest
out s14_waitrequeststd_logic
Definition: avalon_monitor.vhd:335
avalon_monitor.AM1.i8_full
STD_LOGIC i8_full
Definition: avalon_monitor.vhd:856
avalon_monitor.s32_waitrequest
out s32_waitrequeststd_logic
Definition: avalon_monitor.vhd:731
avalon_monitor.m11_readdatavalid
in m11_readdatavalidstd_logic
Definition: avalon_monitor.vhd:281
avalon_monitor.m13_readdata
in m13_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:324
u28
STD_FIFO u28u28
Definition: avalon_monitor.vhd:960
avalon_monitor.s28_writedata
in s28_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:647
avalon_monitor.slave_AvalonMonitor_address
in slave_AvalonMonitor_addressstd_logic_vector( 5 downto 0)
Definition: avalon_monitor.vhd:39
avalon_monitor.s9_write
in s9_writestd_logic
Definition: avalon_monitor.vhd:231
avalon_monitor.m28_writedata
out m28_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:657
avalon_monitor.s32_byteenable
in s32_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:739
avalon_monitor.m19_readdata
in m19_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:456
avalon_monitor.AM1.i5_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i5_data_out
Definition: avalon_monitor.vhd:816
avalon_monitor.m2_byteenable
out m2_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:89
avalon_monitor.slave_AvalonMonitor_write
in slave_AvalonMonitor_writestd_logic
Definition: avalon_monitor.vhd:41
avalon_monitor.s23_burstcount
in s23_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:536
avalon_monitor.AM1.i16_empty
STD_LOGIC i16_empty
Definition: avalon_monitor.vhd:864
avalon_monitor.m7_readdata
in m7_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:192
avalon_monitor.m18_waitrequest
in m18_waitrequeststd_logic
Definition: avalon_monitor.vhd:433
avalon_monitor.AM1.i23_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i23_data_out
Definition: avalon_monitor.vhd:834
avalon_monitor.m9_waitrequest
in m9_waitrequeststd_logic
Definition: avalon_monitor.vhd:235
avalon_monitor.m21_burstcount
out m21_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:502
avalon_monitor.m17_debugaccess
out m17_debugaccessstd_logic
Definition: avalon_monitor.vhd:420
avalon_monitor.m32_read
out m32_readstd_logic
Definition: avalon_monitor.vhd:748
avalon_monitor.m3_readdata
in m3_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:104
avalon_monitor.AM1.i3_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i3_data_out
Definition: avalon_monitor.vhd:814
avalon_monitor.s19_writedata
in s19_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:449
avalon_monitor.s12_writedata
in s12_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:295
avalon_monitor.s1_read
in s1_readstd_logic
Definition: avalon_monitor.vhd:56
avalon_monitor.AM1.i21_almost_full
STD_LOGIC i21_almost_full
Definition: avalon_monitor.vhd:869
avalon_monitor.m7_burstcount
out m7_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:194
avalon_monitor.s10_readdatavalid
out s10_readdatavalidstd_logic
Definition: avalon_monitor.vhd:249
avalon_monitor.AM1.slave_AvalonMonitor_readdata_int
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) slave_AvalonMonitor_readdata_int
Definition: avalon_monitor.vhd:845
avalon_monitor.m7_writedata
out m7_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:195
avalon_monitor.m27_read
out m27_readstd_logic
Definition: avalon_monitor.vhd:638
avalon_monitor.s20_write
in s20_writestd_logic
Definition: avalon_monitor.vhd:473
avalon_monitor.s27_read
in s27_readstd_logic
Definition: avalon_monitor.vhd:628
avalon_monitor.AM1.ADDR_FIFO_29
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 29, slave_AvalonMonitor_address'length) ) ADDR_FIFO_29
Definition: avalon_monitor.vhd:806
avalon_monitor.m15_address
out m15_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:372
avalon_monitor.AM1.i14_almost_full
STD_LOGIC i14_almost_full
Definition: avalon_monitor.vhd:862
avalon_monitor.s9_waitrequest
out s9_waitrequeststd_logic
Definition: avalon_monitor.vhd:225
avalon_monitor.AM1.i20_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i20_address_prev
Definition: avalon_monitor.vhd:831
avalon_monitor.m8_address
out m8_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:218
avalon_monitor.s6_byteenable
in s6_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:167
avalon_monitor.s2_read
in s2_readstd_logic
Definition: avalon_monitor.vhd:78
avalon_monitor.s29_address
in s29_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:670
avalon_monitor.s8_byteenable
in s8_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:211
avalon_monitor.m27_burstcount
out m27_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:634
avalon_monitor.s20_waitrequest
out s20_waitrequeststd_logic
Definition: avalon_monitor.vhd:467
avalon_monitor.AM1.i8_empty
STD_LOGIC i8_empty
Definition: avalon_monitor.vhd:856
avalon_monitor.m21_address
out m21_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:504
avalon_monitor.AM1.ADDR_FIFO_21
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 21, slave_AvalonMonitor_address'length) ) ADDR_FIFO_21
Definition: avalon_monitor.vhd:798
avalon_monitor.AM1.i3_full
STD_LOGIC i3_full
Definition: avalon_monitor.vhd:851
avalon_monitor.s14_write
in s14_writestd_logic
Definition: avalon_monitor.vhd:341
avalon_monitor.s9_byteenable
in s9_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:233
avalon_monitor.m21_readdata
in m21_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:500
avalon_monitor.s32_readdatavalid
out s32_readdatavalidstd_logic
Definition: avalon_monitor.vhd:733
u22
STD_FIFO u22u22
Definition: avalon_monitor.vhd:954
avalon_monitor.AM1.i13_empty
STD_LOGIC i13_empty
Definition: avalon_monitor.vhd:861
avalon_monitor.s2_writedata
in s2_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:75
avalon_monitor.s15_address
in s15_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:362
avalon_monitor.s7_write
in s7_writestd_logic
Definition: avalon_monitor.vhd:187
avalon_monitor.s21_read
in s21_readstd_logic
Definition: avalon_monitor.vhd:496
avalon_monitor.AM1.i23_read_fifo
STD_LOGIC i23_read_fifo
Definition: avalon_monitor.vhd:871
avalon_monitor.s17_address
in s17_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:406
avalon_monitor.s26_write
in s26_writestd_logic
Definition: avalon_monitor.vhd:605
avalon_monitor.m29_readdata
in m29_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:676
avalon_monitor.m12_writedata
out m12_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:305
avalon_monitor.AM1.i6_full
STD_LOGIC i6_full
Definition: avalon_monitor.vhd:854
avalon_monitor.AM1.prev_AvalonMonitor_address
std_logic_vector( slave_AvalonMonitor_address'left downto 0) prev_AvalonMonitor_address
Definition: avalon_monitor.vhd:885
avalon_monitor.s28_burstcount
in s28_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:646
u9
STD_FIFO u9u9
Definition: avalon_monitor.vhd:941
avalon_monitor.s19_readdatavalid
out s19_readdatavalidstd_logic
Definition: avalon_monitor.vhd:447
u13
STD_FIFO u13u13
Definition: avalon_monitor.vhd:945
avalon_monitor.s9_address
in s9_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:230
avalon_monitor.AM1.i24_almost_full
STD_LOGIC i24_almost_full
Definition: avalon_monitor.vhd:872
avalon_monitor.AM1.i2_full
STD_LOGIC i2_full
Definition: avalon_monitor.vhd:850
avalon_monitor.s25_readdatavalid
out s25_readdatavalidstd_logic
Definition: avalon_monitor.vhd:579
avalon_monitor.AM1.i28_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i28_data_out
Definition: avalon_monitor.vhd:839
avalon_monitor.AM1.i29_almost_full
STD_LOGIC i29_almost_full
Definition: avalon_monitor.vhd:877
avalon_monitor.s10_readdata
out s10_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:248
avalon_monitor.s2_byteenable
in s2_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:79
avalon_monitor.m31_debugaccess
out m31_debugaccessstd_logic
Definition: avalon_monitor.vhd:728
avalon_monitor.AM1.i20_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i20_data_out
Definition: avalon_monitor.vhd:831
avalon_monitor.AM1.i29_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i29_data_out
Definition: avalon_monitor.vhd:840
avalon_monitor.s16_waitrequest
out s16_waitrequeststd_logic
Definition: avalon_monitor.vhd:379
avalon_monitor.s24_readdata
out s24_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:556
avalon_monitor.m17_burstcount
out m17_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:414
avalon_monitor.AM1.i7_fifo_store
STD_LOGIC i7_fifo_store
Definition: avalon_monitor.vhd:855
avalon_monitor.m14_readdata
in m14_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:346
avalon_monitor.m17_address
out m17_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:416
avalon_monitor.s11_readdatavalid
out s11_readdatavalidstd_logic
Definition: avalon_monitor.vhd:271
avalon_monitor.s28_waitrequest
out s28_waitrequeststd_logic
Definition: avalon_monitor.vhd:643
avalon_monitor.AM1.i1_full
STD_LOGIC i1_full
Definition: avalon_monitor.vhd:849
avalon_monitor.s12_address
in s12_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:296
avalon_monitor.s9_writedata
in s9_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:229
avalon_monitor.s30_read
in s30_readstd_logic
Definition: avalon_monitor.vhd:694
avalon_monitor.m21_readdatavalid
in m21_readdatavalidstd_logic
Definition: avalon_monitor.vhd:501
avalon_monitor.AM1.i17_fifo_store
STD_LOGIC i17_fifo_store
Definition: avalon_monitor.vhd:865
avalon_monitor.m9_byteenable
out m9_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:243
avalon_monitor.m12_address
out m12_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:306
avalon_monitor.AM1.ADDR_FIFO_3
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 3, slave_AvalonMonitor_address'length) ) ADDR_FIFO_3
Definition: avalon_monitor.vhd:780
avalon_monitor.m30_readdata
in m30_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:698
avalon_monitor.AM1.i27_read_fifo
STD_LOGIC i27_read_fifo
Definition: avalon_monitor.vhd:875
avalon_monitor.AM1.i3_empty
STD_LOGIC i3_empty
Definition: avalon_monitor.vhd:851
avalon_monitor.AM1.i23_full
STD_LOGIC i23_full
Definition: avalon_monitor.vhd:871
avalon_monitor.AM1.i5_almost_full
STD_LOGIC i5_almost_full
Definition: avalon_monitor.vhd:853
avalon_monitor.m7_waitrequest
in m7_waitrequeststd_logic
Definition: avalon_monitor.vhd:191
avalon_monitor.AM1.i8_almost_full
STD_LOGIC i8_almost_full
Definition: avalon_monitor.vhd:856
avalon_monitor.s15_readdatavalid
out s15_readdatavalidstd_logic
Definition: avalon_monitor.vhd:359
avalon_monitor.m2_read
out m2_readstd_logic
Definition: avalon_monitor.vhd:88
avalon_monitor.AM1.i29_empty
STD_LOGIC i29_empty
Definition: avalon_monitor.vhd:877
u1
STD_FIFO u1u1
Definition: avalon_monitor.vhd:919
avalon_monitor.s20_byteenable
in s20_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:475
avalon_monitor.s18_burstcount
in s18_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:426
avalon_monitor.AM1.i28_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i28_address_prev
Definition: avalon_monitor.vhd:839
avalon_monitor.AM1.i10_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i10_data_out
Definition: avalon_monitor.vhd:821
avalon_monitor.s31_waitrequest
out s31_waitrequeststd_logic
Definition: avalon_monitor.vhd:709
avalon_monitor.m6_writedata
out m6_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:173
avalon_monitor.AM1.i25_fifo_store
STD_LOGIC i25_fifo_store
Definition: avalon_monitor.vhd:873
avalon_monitor.s1_readdata
out s1_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:50
avalon_monitor.m32_write
out m32_writestd_logic
Definition: avalon_monitor.vhd:747
avalon_monitor.s3_readdata
out s3_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:94
avalon_monitor.m14_address
out m14_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:350
avalon_monitor.m20_write
out m20_writestd_logic
Definition: avalon_monitor.vhd:483
u3
STD_FIFO u3u3
Definition: avalon_monitor.vhd:935
avalon_monitor.AM1.i28_fifo_store
STD_LOGIC i28_fifo_store
Definition: avalon_monitor.vhd:876
avalon_monitor.m6_address
out m6_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:174
avalon_monitor.s14_address
in s14_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:340
avalon_monitor.m30_burstcount
out m30_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:700
avalon_monitor.ADDRESS_WIDTH
ADDRESS_WIDTHinteger := 32
Definition: avalon_monitor.vhd:23
avalon_monitor.AM1.i25_full
STD_LOGIC i25_full
Definition: avalon_monitor.vhd:873
avalon_monitor.m3_write
out m3_writestd_logic
Definition: avalon_monitor.vhd:109
avalon_monitor.s24_debugaccess
in s24_debugaccessstd_logic
Definition: avalon_monitor.vhd:564
avalon_monitor.AM1.i32_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i32_data_out
Definition: avalon_monitor.vhd:843
avalon_monitor.AM1.i15_read_fifo
STD_LOGIC i15_read_fifo
Definition: avalon_monitor.vhd:863
avalon_monitor.AM1.i20_full
STD_LOGIC i20_full
Definition: avalon_monitor.vhd:868
avalon_monitor.s12_read
in s12_readstd_logic
Definition: avalon_monitor.vhd:298
avalon_monitor.s8_debugaccess
in s8_debugaccessstd_logic
Definition: avalon_monitor.vhd:212
avalon_monitor.m7_debugaccess
out m7_debugaccessstd_logic
Definition: avalon_monitor.vhd:200
avalon_monitor.s3_debugaccess
in s3_debugaccessstd_logic
Definition: avalon_monitor.vhd:102
avalon_monitor.s25_readdata
out s25_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:578
avalon_monitor.AM1.prev_AvalonMonitor_read
std_logic prev_AvalonMonitor_read
Definition: avalon_monitor.vhd:884
avalon_monitor.AM1.i9_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i9_data_out
Definition: avalon_monitor.vhd:820
avalon_monitor.m19_burstcount
out m19_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:458
avalon_monitor.s7_address
in s7_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:186
avalon_monitor.AM1.i6_read_fifo
STD_LOGIC i6_read_fifo
Definition: avalon_monitor.vhd:854
avalon_monitor.s23_readdatavalid
out s23_readdatavalidstd_logic
Definition: avalon_monitor.vhd:535
avalon_monitor.m8_writedata
out m8_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:217
avalon_monitor.m1_read
out m1_readstd_logic
Definition: avalon_monitor.vhd:66
avalon_monitor.SYMBOL_WIDTH
SYMBOL_WIDTHinteger := 8
Definition: avalon_monitor.vhd:22
avalon_monitor.s9_readdatavalid
out s9_readdatavalidstd_logic
Definition: avalon_monitor.vhd:227
avalon_monitor.s12_burstcount
in s12_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:294
avalon_monitor.s16_read
in s16_readstd_logic
Definition: avalon_monitor.vhd:386
avalon_monitor.AM1.i5_read_fifo
STD_LOGIC i5_read_fifo
Definition: avalon_monitor.vhd:853
avalon_monitor.AM1.i21_fifo_store
STD_LOGIC i21_fifo_store
Definition: avalon_monitor.vhd:869
avalon_monitor.s10_read
in s10_readstd_logic
Definition: avalon_monitor.vhd:254
avalon_monitor.s17_debugaccess
in s17_debugaccessstd_logic
Definition: avalon_monitor.vhd:410
avalon_monitor.s1_waitrequest
out s1_waitrequeststd_logic
Definition: avalon_monitor.vhd:49
u23
STD_FIFO u23u23
Definition: avalon_monitor.vhd:955
avalon_monitor.AM1.i24_empty
STD_LOGIC i24_empty
Definition: avalon_monitor.vhd:872
avalon_monitor.AM1.i1_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i1_data_out
Definition: avalon_monitor.vhd:812
avalon_monitor.s17_readdata
out s17_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:402
avalon_monitor.m25_readdatavalid
in m25_readdatavalidstd_logic
Definition: avalon_monitor.vhd:589
avalon_monitor.m20_read
out m20_readstd_logic
Definition: avalon_monitor.vhd:484
avalon_monitor.m13_address
out m13_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:328
avalon_monitor.s6_readdata
out s6_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:160
avalon_monitor.m13_burstcount
out m13_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:326
avalon_monitor.AM1.i8_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i8_address_prev
Definition: avalon_monitor.vhd:819
avalon_monitor.s9_read
in s9_readstd_logic
Definition: avalon_monitor.vhd:232
avalon_monitor.s6_write
in s6_writestd_logic
Definition: avalon_monitor.vhd:165
avalon_monitor.AM1.i27_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i27_data_out
Definition: avalon_monitor.vhd:838
avalon_monitor.AM1.i24_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i24_address_prev
Definition: avalon_monitor.vhd:835
avalon_monitor.s13_burstcount
in s13_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:316
avalon_monitor.AM1.i29_fifo_store
STD_LOGIC i29_fifo_store
Definition: avalon_monitor.vhd:877
avalon_monitor.AM1.i13_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i13_address_prev
Definition: avalon_monitor.vhd:824
avalon_monitor.m31_readdata
in m31_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:720
avalon_monitor.s29_readdata
out s29_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:666
avalon_monitor.AM1.i6_fifo_store
STD_LOGIC i6_fifo_store
Definition: avalon_monitor.vhd:854
u4
STD_FIFO u4u4
Definition: avalon_monitor.vhd:936
avalon_monitor.s31_burstcount
in s31_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:712
avalon_monitor.s5_readdatavalid
out s5_readdatavalidstd_logic
Definition: avalon_monitor.vhd:139
avalon_monitor.m24_byteenable
out m24_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:573
avalon_monitor.s15_writedata
in s15_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:361
avalon_monitor.s4_address
in s4_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:120
avalon_monitor.s30_readdatavalid
out s30_readdatavalidstd_logic
Definition: avalon_monitor.vhd:689
avalon_monitor.AM1.ADDR_FIFO_7
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 7, slave_AvalonMonitor_address'length) ) ADDR_FIFO_7
Definition: avalon_monitor.vhd:784
avalon_monitor.AM1.i12_read_fifo
STD_LOGIC i12_read_fifo
Definition: avalon_monitor.vhd:860
avalon_monitor.s21_writedata
in s21_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:493
avalon_monitor.AM1.ADDR_FIFO_9
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 9, slave_AvalonMonitor_address'length) ) ADDR_FIFO_9
Definition: avalon_monitor.vhd:786
avalon_monitor.AM1.ADDR_FIFO_31
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 31, slave_AvalonMonitor_address'length) ) ADDR_FIFO_31
Definition: avalon_monitor.vhd:808
avalon_monitor.m10_waitrequest
in m10_waitrequeststd_logic
Definition: avalon_monitor.vhd:257
avalon_monitor.s5_burstcount
in s5_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:140
avalon_monitor.AM1.i2_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i2_data_out
Definition: avalon_monitor.vhd:813
avalon_monitor.AM1.i14_read_fifo
STD_LOGIC i14_read_fifo
Definition: avalon_monitor.vhd:862
avalon_monitor.m31_waitrequest
in m31_waitrequeststd_logic
Definition: avalon_monitor.vhd:719
avalon_monitor.s27_address
in s27_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:626
avalon_monitor.m24_debugaccess
out m24_debugaccessstd_logic
Definition: avalon_monitor.vhd:574
avalon_monitor.m20_waitrequest
in m20_waitrequeststd_logic
Definition: avalon_monitor.vhd:477
avalon_monitor.s5_waitrequest
out s5_waitrequeststd_logic
Definition: avalon_monitor.vhd:137
avalon_monitor.s18_readdatavalid
out s18_readdatavalidstd_logic
Definition: avalon_monitor.vhd:425
avalon_monitor.s15_readdata
out s15_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:358
avalon_monitor.s27_readdatavalid
out s27_readdatavalidstd_logic
Definition: avalon_monitor.vhd:623
avalon_monitor.m25_byteenable
out m25_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:595
avalon_monitor.s20_address
in s20_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:472
avalon_monitor.AM1.i30_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i30_address_prev
Definition: avalon_monitor.vhd:841
avalon_monitor.s19_debugaccess
in s19_debugaccessstd_logic
Definition: avalon_monitor.vhd:454
avalon_monitor.m20_byteenable
out m20_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:485
avalon_monitor.m32_readdatavalid
in m32_readdatavalidstd_logic
Definition: avalon_monitor.vhd:743
avalon_monitor.m16_waitrequest
in m16_waitrequeststd_logic
Definition: avalon_monitor.vhd:389
avalon_monitor.s1_write
in s1_writestd_logic
Definition: avalon_monitor.vhd:55
avalon_monitor.m4_write
out m4_writestd_logic
Definition: avalon_monitor.vhd:131
avalon_monitor.m13_readdatavalid
in m13_readdatavalidstd_logic
Definition: avalon_monitor.vhd:325
avalon_monitor.s22_read
in s22_readstd_logic
Definition: avalon_monitor.vhd:518
avalon_monitor.s12_waitrequest
out s12_waitrequeststd_logic
Definition: avalon_monitor.vhd:291
avalon_monitor.s24_write
in s24_writestd_logic
Definition: avalon_monitor.vhd:561
avalon_monitor.s2_debugaccess
in s2_debugaccessstd_logic
Definition: avalon_monitor.vhd:80
avalon_monitor.m27_readdatavalid
in m27_readdatavalidstd_logic
Definition: avalon_monitor.vhd:633
avalon_monitor.m11_write
out m11_writestd_logic
Definition: avalon_monitor.vhd:285
avalon_monitor.AM1.i11_almost_full
STD_LOGIC i11_almost_full
Definition: avalon_monitor.vhd:859
avalon_monitor.AM1.i28_read_fifo
STD_LOGIC i28_read_fifo
Definition: avalon_monitor.vhd:876
avalon_monitor.AM1.i16_full
STD_LOGIC i16_full
Definition: avalon_monitor.vhd:864
avalon_monitor.AM1.i18_empty
STD_LOGIC i18_empty
Definition: avalon_monitor.vhd:866
avalon_monitor.s24_byteenable
in s24_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:563
avalon_monitor.m14_byteenable
out m14_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:353
avalon_monitor.AM1.i14_full
STD_LOGIC i14_full
Definition: avalon_monitor.vhd:862
avalon_monitor.AM1.i22_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i22_address_prev
Definition: avalon_monitor.vhd:833
avalon_monitor.s15_burstcount
in s15_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:360
avalon_monitor.s25_write
in s25_writestd_logic
Definition: avalon_monitor.vhd:583
avalon_monitor.m28_byteenable
out m28_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:661
avalon_monitor.m27_waitrequest
in m27_waitrequeststd_logic
Definition: avalon_monitor.vhd:631
avalon_monitor.s28_read
in s28_readstd_logic
Definition: avalon_monitor.vhd:650
avalon_monitor.m6_read
out m6_readstd_logic
Definition: avalon_monitor.vhd:176
avalon_monitor.s23_debugaccess
in s23_debugaccessstd_logic
Definition: avalon_monitor.vhd:542
avalon_monitor.s26_address
in s26_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:604
avalon_monitor.m13_debugaccess
out m13_debugaccessstd_logic
Definition: avalon_monitor.vhd:332
avalon_monitor.m11_waitrequest
in m11_waitrequeststd_logic
Definition: avalon_monitor.vhd:279
avalon_monitor.AM1.i1_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i1_address_prev
Definition: avalon_monitor.vhd:812
avalon_monitor.s23_byteenable
in s23_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:541
avalon_monitor.s21_readdata
out s21_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:490
avalon_monitor.AM1.i16_fifo_store
STD_LOGIC i16_fifo_store
Definition: avalon_monitor.vhd:864
avalon_monitor.s30_write
in s30_writestd_logic
Definition: avalon_monitor.vhd:693
avalon_monitor.AM1.i15_almost_full
STD_LOGIC i15_almost_full
Definition: avalon_monitor.vhd:863
STD_FIFO.Almost_Full
out Almost_FullSTD_LOGIC
Definition: STD_FIFO.vhd:18
avalon_monitor.s8_readdata
out s8_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:204
avalon_monitor.s14_byteenable
in s14_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:343
avalon_monitor.AM1.ADDR_FIFO_5
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 5, slave_AvalonMonitor_address'length) ) ADDR_FIFO_5
Definition: avalon_monitor.vhd:782
avalon_monitor.m15_waitrequest
in m15_waitrequeststd_logic
Definition: avalon_monitor.vhd:367
avalon_monitor.m14_readdatavalid
in m14_readdatavalidstd_logic
Definition: avalon_monitor.vhd:347
avalon_monitor.m2_waitrequest
in m2_waitrequeststd_logic
Definition: avalon_monitor.vhd:81
avalon_monitor.m26_byteenable
out m26_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:617
avalon_monitor.m5_readdata
in m5_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:148
avalon_monitor.m28_readdatavalid
in m28_readdatavalidstd_logic
Definition: avalon_monitor.vhd:655
avalon_monitor.m3_debugaccess
out m3_debugaccessstd_logic
Definition: avalon_monitor.vhd:112
avalon_monitor.m29_address
out m29_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:680
avalon_monitor.AM1.i3_almost_full
STD_LOGIC i3_almost_full
Definition: avalon_monitor.vhd:851
avalon_monitor.AM1.i17_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i17_address_prev
Definition: avalon_monitor.vhd:828
avalon_monitor.AM1.i20_read_fifo
STD_LOGIC i20_read_fifo
Definition: avalon_monitor.vhd:868
avalon_monitor.m10_byteenable
out m10_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:265
avalon_monitor.s31_readdatavalid
out s31_readdatavalidstd_logic
Definition: avalon_monitor.vhd:711
avalon_monitor.AM1.i5_full
STD_LOGIC i5_full
Definition: avalon_monitor.vhd:853
avalon_monitor.AM1.i14_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i14_data_out
Definition: avalon_monitor.vhd:825
avalon_monitor.AM1.i25_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i25_data_out
Definition: avalon_monitor.vhd:836
avalon_monitor.AM1.i31_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i31_data_out
Definition: avalon_monitor.vhd:842
avalon_monitor.AM1.i11_fifo_store
STD_LOGIC i11_fifo_store
Definition: avalon_monitor.vhd:859
avalon_monitor.AM1.i12_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i12_address_prev
Definition: avalon_monitor.vhd:823
avalon_monitor.s18_waitrequest
out s18_waitrequeststd_logic
Definition: avalon_monitor.vhd:423
u11
STD_FIFO u11u11
Definition: avalon_monitor.vhd:943
avalon_monitor.m9_debugaccess
out m9_debugaccessstd_logic
Definition: avalon_monitor.vhd:244
avalon_monitor.m12_readdata
in m12_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:302
avalon_monitor.BYTEEN_WIDTH
BYTEEN_WIDTHinteger := 4
Definition: avalon_monitor.vhd:25
avalon_monitor.s3_waitrequest
out s3_waitrequeststd_logic
Definition: avalon_monitor.vhd:93
avalon_monitor.m29_burstcount
out m29_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:678
avalon_monitor.s15_read
in s15_readstd_logic
Definition: avalon_monitor.vhd:364
avalon_monitor.s26_readdata
out s26_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:600
avalon_monitor.s20_writedata
in s20_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:471
avalon_monitor.s8_write
in s8_writestd_logic
Definition: avalon_monitor.vhd:209
avalon_monitor.m8_readdata
in m8_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:214
avalon_monitor.AM1.i4_read_fifo
STD_LOGIC i4_read_fifo
Definition: avalon_monitor.vhd:852
avalon_monitor.s30_writedata
in s30_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:691
avalon_monitor.s25_waitrequest
out s25_waitrequeststd_logic
Definition: avalon_monitor.vhd:577
avalon_monitor.s17_write
in s17_writestd_logic
Definition: avalon_monitor.vhd:407
avalon_monitor.m3_address
out m3_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:108
avalon_monitor.s4_writedata
in s4_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:119
avalon_monitor.AM1.i10_fifo_store
STD_LOGIC i10_fifo_store
Definition: avalon_monitor.vhd:858
avalon_monitor.m26_readdata
in m26_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:610
avalon_monitor.m6_write
out m6_writestd_logic
Definition: avalon_monitor.vhd:175
avalon_monitor.AM1.i8_read_fifo
STD_LOGIC i8_read_fifo
Definition: avalon_monitor.vhd:856
avalon_monitor.AM1.i19_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i19_data_out
Definition: avalon_monitor.vhd:830
avalon_monitor.s27_byteenable
in s27_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:629
avalon_monitor.AM1.i3_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i3_address_prev
Definition: avalon_monitor.vhd:814
avalon_monitor.m14_writedata
out m14_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:349
avalon_monitor.AM1.i10_empty
STD_LOGIC i10_empty
Definition: avalon_monitor.vhd:858
avalon_monitor.AM1.i26_empty
STD_LOGIC i26_empty
Definition: avalon_monitor.vhd:874
avalon_monitor.m3_writedata
out m3_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:107
avalon_monitor.s27_burstcount
in s27_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:624
avalon_monitor.m7_read
out m7_readstd_logic
Definition: avalon_monitor.vhd:198
avalon_monitor.s16_writedata
in s16_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:383
avalon_monitor.s29_burstcount
in s29_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:668
avalon_monitor.m2_writedata
out m2_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:85
avalon_monitor.AM1.ADDR_FIFO_16
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 16, slave_AvalonMonitor_address'length) ) ADDR_FIFO_16
Definition: avalon_monitor.vhd:793
avalon_monitor.s3_writedata
in s3_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:97
avalon_monitor.AM1.ADDR_FIFO_17
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 17, slave_AvalonMonitor_address'length) ) ADDR_FIFO_17
Definition: avalon_monitor.vhd:794
avalon_monitor.m4_address
out m4_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:130
avalon_monitor.m18_readdata
in m18_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:434
avalon_monitor.AM1.i7_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i7_data_out
Definition: avalon_monitor.vhd:818
avalon_monitor.AM1.i13_full
STD_LOGIC i13_full
Definition: avalon_monitor.vhd:861
avalon_monitor.s29_read
in s29_readstd_logic
Definition: avalon_monitor.vhd:672
avalon_monitor.m28_burstcount
out m28_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:656
u14
STD_FIFO u14u14
Definition: avalon_monitor.vhd:946
avalon_monitor.m30_read
out m30_readstd_logic
Definition: avalon_monitor.vhd:704
avalon_monitor.s2_burstcount
in s2_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:74
avalon_monitor.AM1.i25_read_fifo
STD_LOGIC i25_read_fifo
Definition: avalon_monitor.vhd:873
avalon_monitor.m26_readdatavalid
in m26_readdatavalidstd_logic
Definition: avalon_monitor.vhd:611
avalon_monitor.m12_readdatavalid
in m12_readdatavalidstd_logic
Definition: avalon_monitor.vhd:303
avalon_monitor.AM1.i11_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i11_address_prev
Definition: avalon_monitor.vhd:822
avalon_monitor.s2_address
in s2_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:76
avalon_monitor.s23_readdata
out s23_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:534
u21
STD_FIFO u21u21
Definition: avalon_monitor.vhd:953
STD_FIFO.ReadEn
in ReadEnSTD_LOGIC
Definition: STD_FIFO.vhd:15
avalon_monitor.s14_debugaccess
in s14_debugaccessstd_logic
Definition: avalon_monitor.vhd:344
avalon_monitor.m9_readdata
in m9_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:236
avalon_monitor.s2_readdatavalid
out s2_readdatavalidstd_logic
Definition: avalon_monitor.vhd:73
avalon_monitor.AM1.i23_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i23_address_prev
Definition: avalon_monitor.vhd:834
avalon_monitor.m9_address
out m9_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:240
avalon_monitor.m14_burstcount
out m14_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:348
avalon_monitor.AM1.i23_fifo_store
STD_LOGIC i23_fifo_store
Definition: avalon_monitor.vhd:871
avalon_monitor.m32_readdata
in m32_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:742
avalon_monitor.m22_burstcount
out m22_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:524
avalon_monitor.AM1.i15_fifo_store
STD_LOGIC i15_fifo_store
Definition: avalon_monitor.vhd:863
avalon_monitor.s31_byteenable
in s31_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:717
avalon_monitor.AM1.i32_fifo_store
STD_LOGIC i32_fifo_store
Definition: avalon_monitor.vhd:880
avalon_monitor.AM1.i27_address_prev
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i27_address_prev
Definition: avalon_monitor.vhd:838
avalon_monitor.AM1.i19_fifo_store
STD_LOGIC i19_fifo_store
Definition: avalon_monitor.vhd:867
avalon_monitor.s16_burstcount
in s16_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:382
avalon_monitor.m27_readdata
in m27_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:632
avalon_monitor.m18_readdatavalid
in m18_readdatavalidstd_logic
Definition: avalon_monitor.vhd:435
avalon_monitor.s2_write
in s2_writestd_logic
Definition: avalon_monitor.vhd:77
avalon_monitor.s6_writedata
in s6_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:163
avalon_monitor.m19_address
out m19_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:460
avalon_monitor.s9_debugaccess
in s9_debugaccessstd_logic
Definition: avalon_monitor.vhd:234
avalon_monitor.AM1.ADDR_FIFO_18
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 18, slave_AvalonMonitor_address'length) ) ADDR_FIFO_18
Definition: avalon_monitor.vhd:795
avalon_monitor.m30_writedata
out m30_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:701
avalon_monitor.s27_readdata
out s27_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:622
avalon_monitor.m14_read
out m14_readstd_logic
Definition: avalon_monitor.vhd:352
avalon_monitor.s14_writedata
in s14_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:339
avalon_monitor.m5_write
out m5_writestd_logic
Definition: avalon_monitor.vhd:153
avalon_monitor.s30_readdata
out s30_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:688
avalon_monitor.m16_writedata
out m16_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:393
avalon_monitor.m15_writedata
out m15_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:371
avalon_monitor.m1_burstcount
out m1_burstcountstd_logic_vector( BURSTCOUNT_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:62
avalon_monitor.m19_byteenable
out m19_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:463
avalon_monitor.s31_read
in s31_readstd_logic
Definition: avalon_monitor.vhd:716
avalon_monitor.m27_writedata
out m27_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:635
avalon_monitor.s10_write
in s10_writestd_logic
Definition: avalon_monitor.vhd:253
avalon_monitor.s10_debugaccess
in s10_debugaccessstd_logic
Definition: avalon_monitor.vhd:256
avalon_monitor.s4_write
in s4_writestd_logic
Definition: avalon_monitor.vhd:121
avalon_monitor.m26_waitrequest
in m26_waitrequeststd_logic
Definition: avalon_monitor.vhd:609
avalon_monitor.AM1.i4_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i4_data_out
Definition: avalon_monitor.vhd:815
avalon_monitor.m25_read
out m25_readstd_logic
Definition: avalon_monitor.vhd:594
avalon_monitor.m29_read
out m29_readstd_logic
Definition: avalon_monitor.vhd:682
avalon_monitor.s7_byteenable
in s7_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:189
avalon_monitor.s4_read
in s4_readstd_logic
Definition: avalon_monitor.vhd:122
avalon_monitor.s15_debugaccess
in s15_debugaccessstd_logic
Definition: avalon_monitor.vhd:366
avalon_monitor.AM1.ADDR_FIFO_6
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 6, slave_AvalonMonitor_address'length) ) ADDR_FIFO_6
Definition: avalon_monitor.vhd:783
avalon_monitor.m23_readdatavalid
in m23_readdatavalidstd_logic
Definition: avalon_monitor.vhd:545
avalon_monitor.AM1.i13_data_out
STD_LOGIC_VECTOR( ADDRESS_WIDTH- 1 downto 0) i13_data_out
Definition: avalon_monitor.vhd:824
avalon_monitor.s19_readdata
out s19_readdatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:446
avalon_monitor.AM1.ADDR_FIFO_10
std_logic_vector( slave_AvalonMonitor_address'left downto 0) := std_logic_vector(to_unsigned( 10, slave_AvalonMonitor_address'length) ) ADDR_FIFO_10
Definition: avalon_monitor.vhd:787
avalon_monitor.s23_read
in s23_readstd_logic
Definition: avalon_monitor.vhd:540
avalon_monitor.s12_debugaccess
in s12_debugaccessstd_logic
Definition: avalon_monitor.vhd:300
avalon_monitor.m15_byteenable
out m15_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:375
avalon_monitor.AM1.i32_read_fifo
STD_LOGIC i32_read_fifo
Definition: avalon_monitor.vhd:880
avalon_monitor.s28_write
in s28_writestd_logic
Definition: avalon_monitor.vhd:649
avalon_monitor.m28_address
out m28_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:658
avalon_monitor.m26_address
out m26_addressstd_logic_vector( ADDRESS_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:614
avalon_monitor.s15_byteenable
in s15_byteenablestd_logic_vector( BYTEEN_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:365
avalon_monitor.m22_readdatavalid
in m22_readdatavalidstd_logic
Definition: avalon_monitor.vhd:523
avalon_monitor.s6_waitrequest
out s6_waitrequeststd_logic
Definition: avalon_monitor.vhd:159
avalon_monitor.AM1.i16_read_fifo
STD_LOGIC i16_read_fifo
Definition: avalon_monitor.vhd:864
avalon_monitor.s11_debugaccess
in s11_debugaccessstd_logic
Definition: avalon_monitor.vhd:278
avalon_monitor.m3_waitrequest
in m3_waitrequeststd_logic
Definition: avalon_monitor.vhd:103
avalon_monitor.s18_write
in s18_writestd_logic
Definition: avalon_monitor.vhd:429
avalon_monitor.m5_writedata
out m5_writedatastd_logic_vector( DATA_WIDTH- 1 downto 0)
Definition: avalon_monitor.vhd:151
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