GeMRTOS: Multiprocessor RTOS – Reference Design

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Step 7: Program the FPGA device

Programming the FPGA can be done using the Quartus Prime Programmer tool or by running the following command:

quartus_pgm.exe -m JTAG -o "p;output_files/<Quartus_Prime_Project_Name>. sof"

For devices where the FPGA configuration is second in the programming chain, use:

quartus_pgm.exe -m JTAG -o "p;output_files/<Quartus_Prime_Project_Name>. sof@2"

Note: After successful execution, the FPGA will be configured with the hardware architecture. The system’s processors and JTAG UARTs can be verified by running:

jtagconfig.exe -n

showing the processors and JTAG UARTs accessible through the JTAG interface:

1) USB-Blaster [USB-0]
  020F30DD   10CL025(Y|Z)/EP3C25/EP4CE22
    Design hash    0CBAE831A5A1AE5AA13C
    + Node 19104600  Nios II #0
    + Node 19104601  Nios II #1
    + Node 19104602  Nios II #2
    + Node 0C006E00  JTAG UART #0
    + Node 0C006E01  JTAG UART #1
    + Node 0C206E00  JTAG PHY #0
    + Node 0C006E02  JTAG UART #2
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