GeMRTOS Controller: Complete FPGA RTOS Hardware Guide

GeMRTOS Controller is the central hardware component responsible for managing and synchronizing all hardware events in a GeMRTOS multiprocessor RTOS running on Altera FPGA platforms with Nios II or Nios V processors. It coordinates interrupt routing, hardware mutex access, and real-time event scheduling across all processors in the system. This guide covers the complete GeMRTOS Controller architecture, its six internal modules, all hardware registers, and the macro instruction set used to configure and interact with the controller.

GeMRTOS Controller Architecture #

As shown in FIG. 1, the GeMRTOS Controller integrates six functional modules connected through an addressable control logic (212):

• Interrupt Input Module (200) — receives device interrupt requests (DIRQs) via device interrupt request inputs (DIRQIs) (201–203)
• Interrupt Output Module (204) — sends processor interrupt requests (PIRQs) via processor interrupt request outputs (PIRQOs) (205–207)
• Controller Registers (208) — memory-mapped registers for configuring controller behavior
• Time Module (209) — manages system time and timed events
• Mutex Module (210) — provides hardware-enforced mutual exclusion across processors
• Event Module (211) — prioritizes and dispatches hardware events to processors

The addressable control logic includes an interface element (213) and a decoder element (214) that expose all controller registers to the processor bus through unique memory-mapped addresses.

Controller Registers #

The behavior of the GeMRTOS Controller is determined by its set of hardware registers (208). Each register is assigned a unique memory-mapped address, accessible for both read and write operations through the interface element. For example, the R_CTRL register configures core controller functions such as enabling or disabling frozen mode. GeMRTOS macro instructions are provided to access all registers without requiring direct address manipulation.

Hardware Mutex Module #

In a multiprocessor FPGA system, coherency between processors in critical sections must be enforced at the hardware level. The GeMRTOS Controller’s mutex module provides this enforcement through the R_MTX_PRC_GRN register (the mutex register), which controls exclusive access to critical sections across all processors.

How Does the GeMRTOS Hardware Mutex Work? #

The R_MTX_PRC_GRN register can hold three types of values:

• 0 — No processor holds the critical section; any processor may request the mutex.
• 1 to N — The critical section is granted to the processor whose CPUID matches the register value.
• MTX_BLCK — The critical section is blocked while the R_MTX_CLR_CNT register is non-zero. This prevents starvation by queuing the next processor in the R_MTX_NXT_PRC register, avoiding active competition among processors.

For efficient mutex acquisition, each processor sets its corresponding bit in the R_MTX_RSV_PRC register using the GeMRTOS_USER_CRITICAL_SECTION_GET macro. The GeMRTOS Controller then halts the processor (via a wait_request signal) until the mutex is granted. The processor holding the critical section releases it with the GeMRTOS_USER_CRITICAL_SECTION_RELEASE macro.

Time Management Module #

The GeMRTOS Controller time module provides a flexible, prescaled time base for all RTOS timing operations. The system clock is divided through the R_TM_PSC_CNT up-counter register, and all time references in GeMRTOS derive from this prescaled signal. The prescale value is configured with the GeMRTOS_CMD_SET_TIME_PRESCALE(scale) macro instruction.

What Are the GeMRTOS Controller Time Modes? #

The GeMRTOS Controller operates in one of two time modes at any given moment:

• Unfrozen mode — the normal operating mode. The up-counter R_TM_CNT (the time counting register) increments at the system time unit rate. This mode is active while: (R_FRZ_TM_THR + R_NXT_EVN_CNT < R_TM_CNT AND C1_FRZ_MDE_ENB == 1) OR C1_FRZ_MDE_ENB == 0
• Frozen mode — activated when frozen mode is enabled (C1_FRZ_MDE_ENB == 1) and the next time event in R_NXT_EVN_CNT remains unprocessed for longer than the threshold in R_FRZ_TM_THR. R_TM_CNT is frozen and the R_FRZ_TM_CNT register (frozen time counting register) increments instead, preventing event backlogs from cascading.

During runtime, unfrozen mode is standard. Each time R_TM_CNT reaches the value in R_NXT_EVN_CNT, a time event occurs. The processor executing the associated task is interrupted; otherwise, the lowest-priority system processor handles the event. When all time events are processed (R_TM_CNT > R_NXT_EVN_CNT), the controller automatically returns to unfrozen mode.

Unfrozen/Frozen Mode Macro Instructions #

Interrupt Management: Input and Output Modules #

Most embedded RTOS applications consist of tasks prioritized for execution on system processors. When events occur, a processor must be interrupted to run the corresponding event handler. The GeMRTOS Controller classifies events that generate processor interrupt requests (PIRQs) into three categories:

• Time events — configured to occur at a specific system time. A time event fires when R_NXT_EVN_CNT >= R_TM_CNT. The C1_EVN_TM_OCC signal is asserted when this condition is true.
• Device interrupt requests (DIRQs) — generated by I/O peripheral devices. A DIRQ produces a PIRQ when the device has a pending request and its bit in the R_IRQ_ENB register is enabled.
• Internal interrupt triggers — a processor may interrupt another by setting its bit in the R_TRG_PRC_INT register (bit 0 = processor 1, bit 1 = processor 2, etc.).

A processor is interrupted (its PIRQ asserted) when the critical section is not held, its interrupt is enabled in R_INT_ENB, and one of the following is true:

• The processor is executing the task tied to the next time event (R_NXT_TM_EVN_PRC bit set) and a time event occurred (C1_EVN_TM_OCC asserted), or
• The processor is executing the lowest-priority task (R_LOW_PRI_PRC bit set) and an IRQ is pending (C1_IRQ_PND set), or
• The processor is executing the lowest-priority task and a time event occurred with no processor assigned to handle it.

PIRQOs are registered outputs to prevent spurious triggers. The R_IRQ_PND register tracks pending processor interrupts, cleared by each processor during ISR execution via R_INT_CLR. When a processor’s ISR runs, its interrupt is disabled in the GeMRTOS Controller (R_INT_ENB), and the hardware mutex is requested before entering the critical section.

I/O Interrupt Macro Instructions #

Event Module #

The GeMRTOS Controller event module maintains system consistency by sorting concurrent hardware events and dispatching them in deterministic priority order. When a processor is interrupted, it reads the event code from the R_LST_EVN register using the GeMRTOS_CMD_EVN_OCC instruction. If multiple events are pending simultaneously, the event module assigns the highest-priority (lowest sorted order) event code to R_LST_EVN.

Event Module Macro Instruction #

Key Takeaways #

• The GeMRTOS Controller centralizes interrupt management, mutual exclusion, and time event scheduling for multiprocessor FPGA RTOS systems on Altera Nios II/Nios V platforms.
• Its hardware mutex module eliminates active competition between processors using the R_MTX_RSV_PRC reservation mechanism and processor halt-on-wait.
• The time module supports unfrozen and frozen modes to prevent event-processing backlogs from destabilizing the system.
• Three interrupt event types (time, DIRQ, internal trigger) are routed to the lowest-priority processor unless a specific processor is assigned to the next event.
• All controller functions are accessible through memory-mapped registers and GeMRTOS macro instructions — no direct register address manipulation is required in application code.