The Platform Designer flow for GeMRTOS covers both hardware and software implementation for Intel FPGA platforms with Nios V processors. Platform Designer — part of the Quartus Prime suite — is used to create the embedded system, which is then integrated into a hardware design, compiled, and programmed onto the FPGA. A Board Support Package (BSP) provides the Hardware Abstraction Layer (HAL) for the software application, which is compiled with standard gcc tools. The gemrtos_build.sh script automates all steps in the flow.
Design Flow Overview #
The complete Platform Designer flow for a GeMRTOS Nios V system consists of six sequential stages, from embedded system design through to FPGA programming and software execution:
Step-by-Step Platform Designer Flow #
- Create the embedded system with Platform Designer — Use the Platform Designer tool (formerly Qsys) within Quartus Prime to define the embedded system: add and configure the Nios V processor, memory, and peripheral IP cores, and generate the system interconnect.
- Integrate into the hardware design — Incorporate the Platform Designer-generated system into the top-level Quartus Prime hardware design. Connect external I/O signals and finalize the FPGA pin assignments.
- Compile the hardware design with Quartus Prime — Run the Quartus Prime compilation flow (Analysis & Synthesis, Fitter, Assembler) to produce the FPGA configuration file (
.sof/.rbf). - Generate the Board Support Package (BSP) — Use Intel’s BSP generation tools to produce the Hardware Abstraction Layer (HAL) libraries and configuration headers tailored to the hardware design. The BSP provides the low-level drivers and OS integration layer for the GeMRTOS software.
- Compile the software application with gcc — Build the GeMRTOS application using the Nios V gcc toolchain, linking against the generated BSP libraries to produce the executable (
.elf). - Program the FPGA and run the application — Use Quartus Programmer to download the hardware configuration to the FPGA, then load and execute the software application on the Nios V processor.
Automating the Flow with gemrtos_build.sh #
The gemrtos_build.sh script automates all steps in the Platform Designer design flow — from BSP generation and software compilation through to FPGA programming. Running the script eliminates the need to manually invoke each tool in sequence, reducing build time and the risk of configuration errors between steps. It is the recommended way to rebuild a GeMRTOS project after hardware or software changes.
Key Takeaways #
- The Platform Designer flow for GeMRTOS Nios V combines hardware design in Quartus Prime with BSP generation and gcc-based software compilation into a single end-to-end workflow.
- Platform Designer (part of the Quartus Prime suite) handles embedded system creation — Nios V processor, memory, and peripheral IP — and generates the system interconnect automatically.
- The BSP produced by Intel tools provides the HAL layer that bridges GeMRTOS software to the specific hardware configuration; it must be regenerated whenever the hardware design changes.
- The final FPGA configuration is programmed via Quartus Programmer; the software application (
.elf) is then downloaded and executed on the Nios V processor. - gemrtos_build.sh automates the complete flow, making it the recommended entry point for building and deploying a GeMRTOS Nios V system.
